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/linux-6.8/Documentation/devicetree/bindings/pci/
Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
16 Each PCIe node needs to have property msi-parent that points to an MSI
25 compatible = "apm,xgene1-msi";
[all …]
/linux-6.8/Documentation/devicetree/bindings/pinctrl/
Dmarvell,mvebu-pinctrl.txt3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
24 valid pin/pin group names and available function names for each SoC.
30 reg = <0x12100 0x100>;
31 reg-shift = <2>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/rtc/
Drtc-mt7622.txt1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
6 - reg : Specifies base physical address and size of the registers;
7 - interrupts : Should contain the interrupt for RTC alarm;
8 - clocks : Specifies list of clock specifiers, corresponding to
9 entries in clock-names property;
10 - clock-names : Should contain "rtc" entries
15 compatible = "mediatek,mt7622-rtc",
16 "mediatek,soc-rtc";
[all …]
Dnxp,lpc1788-rtc.txt1 NXP LPC1788 real-time clock
7 - compatible : must contain "nxp,lpc1788-rtc"
8 - reg : Specifies base physical address and size of the registers.
9 - interrupts : A single interrupt specifier.
10 - clocks : Must contain clock specifiers for rtc and register clock
11 - clock-names : Must contain "rtc" and "reg"
12 See ../clocks/clock-bindings.txt for details.
16 compatible = "nxp,lpc1788-rtc";
17 reg = <0x40046000 0x1000>;
20 clock-names = "rtc", "reg";
/linux-6.8/Documentation/devicetree/bindings/watchdog/
Dsprd-wdt.txt4 - compatible : Should be "sprd,sp9860-wdt".
5 - reg : Specifies base physical address and size of the registers.
6 - interrupts : Exactly one interrupt specifier.
7 - timeout-sec : Contain the default watchdog timeout in seconds.
8 - clock-names : Contain the input clock names.
9 - clocks : Phandles to input clocks.
13 compatible = "sprd,sp9860-wdt";
14 reg = <0 0x40310000 0 0x1000>;
16 timeout-sec = <12>;
17 clock-names = "enable", "rtc_enable";
/linux-6.8/arch/arm/boot/dts/nxp/imx/
Dimx7d-flex-concentrator.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "imx7d-tqma7.dtsi"
14 /delete-node/ &ds1339;
18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d";
22 /* 1024 MB - TQMa7D board configuration */
23 reg = <0x80000000 0x40000000>;
26 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
27 compatible = "regulator-fixed";
28 regulator-name = "VBUS_USBOTG2";
[all …]
Dimx6dl-mamoj.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
19 reg = <0x10000000 0>;
22 backlight_lcd: backlight-lcd {
23 compatible = "pwm-backlight";
24 pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
25 brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
26 default-brightness-level = <7>;
[all …]
Dimx6ul-tx6ul-mainboard.dts2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
44 #include "imx6ul-tx6ul.dtsi"
47 model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
48 compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
51 lcdif-24bit-pins-a = &pinctrl_disp0_3;
53 /delete-property/ mmc1;
57 /delete-node/ sound;
61 xceiver-supply = <&reg_3v3>;
[all …]
Dimx6q-marsboard.dts2 * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
44 #include <dt-bindings/gpio/gpio.h>
48 compatible = "embest,imx6q-marsboard", "fsl,imx6q";
52 reg = <0x10000000 0x40000000>;
55 reg_3p3v: regulator-3p3v {
56 compatible = "regulator-fixed";
57 regulator-name = "3P3V";
58 regulator-min-microvolt = <3300000>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
29 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
[all …]
/linux-6.8/drivers/clk/keystone/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
87 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
88 val = readl(pll_data->pllm); in clk_pllclk_recalc()
[all …]
/linux-6.8/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Dam335x-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
22 cpu0-supply = <&vdd1_reg>;
28 reg = <0x80000000 0x10000000>; /* 256 MB */
32 compatible = "regulator-fixed";
33 regulator-name = "vcc5v";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 regulator-boot-on;
[all …]
/linux-6.8/arch/arm/boot/dts/nxp/mxs/
Dimx23-stmp378x_devb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
11 compatible = "fsl,stmp378x-devb", "fsl,imx23";
15 reg = <0x40000000 0x04000000>;
21 compatible = "fsl,imx23-mmc";
22 pinctrl-names = "default";
23 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
24 bus-width = <4>;
25 wp-gpios = <&gpio1 30 0>;
26 vmmc-supply = <&reg_vddio_sd0>;
[all …]
/linux-6.8/arch/arm64/boot/dts/rockchip/
Drk3399-rock-pi-4b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3399-rock-pi-4.dtsi"
9 #include "rk3399-opp.dtsi"
24 compatible = "brcm,bcm4329-fmac";
25 reg = <1>;
26 interrupt-parent = <&gpio0>;
28 interrupt-names = "host-wake";
29 pinctrl-names = "default";
30 pinctrl-0 = <&wifi_host_wake_l>;
[all …]
/linux-6.8/arch/arm/boot/dts/microchip/
Dsama5d3_can.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
35 compatible = "atmel,at91sam9x5-can";
36 reg = <0xf000c000 0x300>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_can0_rx_tx>;
41 clock-names = "can_clk";
46 compatible = "atmel,at91sam9x5-can";
[all …]
Dat91sam9x5_can.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-can";
17 reg = <0xf8000000 0x300>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
22 clock-names = "can_clk";
27 compatible = "atmel,at91sam9x5-can";
[all …]
/linux-6.8/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
21 - $ref: /schemas/spi/spi-controller.yaml#
26 - enum:
27 - mediatek,mt8173-nor
28 - mediatek,mt8186-nor
[all …]
Dnuvoton,wpcm450-fiu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
13 - $ref: /schemas/spi/spi-controller.yaml#
17 const: nuvoton,wpcm450-fiu
19 reg:
21 - description: FIU registers
22 - description: Memory-mapped flash contents
[all …]
/linux-6.8/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
[all …]
/linux-6.8/Documentation/devicetree/bindings/dma/
Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
25 reg:
[all …]
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-370-seagate-personal-cloud.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
15 #include "armada-370.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
26 reg = <0x00000000 0x20000000>; /* 512 MB */
33 internal-regs {
34 coherency-fabric@20200 {
35 broken-idle;
[all …]
Dorion5x-netgear-wnr854t.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include "orion5x-mv88f5181.dtsi"
11 model = "Netgear WNR854-t";
12 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
20 reg = <0x00000000 0x2000000>; /* 32 MB */
24 stdout-path = "serial0:115200n8";
33 gpio-keys {
[all …]
/linux-6.8/Documentation/devicetree/bindings/arm/
Darm,coresight-etm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
31 - arm,coresight-etm3x
[all …]
/linux-6.8/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-bananapi-cm4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12b-a311d.dtsi"
7 #include <dt-bindings/gpio/meson-g12a-gpio.h>
16 stdout-path = "serial0:115200n8";
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc";
21 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
26 reg = <0x0 0x0 0x0 0x40000000>;
29 sdio_pwrseq: sdio-pwrseq {
30 compatible = "mmc-pwrseq-simple";
[all …]

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