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/linux-5.10/arch/arm/boot/dts/
Dsun5i-gr8-evb.dts5 * Mylène Josserand <mylene.josserand@free-electrons.com>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun5i-gr8.dtsi"
48 #include "sunxi-common-regulators.dtsi"
50 #include <dt-bindings/gpio/gpio.h>
51 #include <dt-bindings/input/input.h>
52 #include <dt-bindings/interrupt-controller/irq.h>
55 model = "NextThing GR8-EVB";
56 compatible = "nextthing,gr8-evb", "nextthing,gr8";
[all …]
Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
14 stdout-path = "serial2:115200n8";
23 reg = <0x0 0x0 0x0 0x80000000>;
27 power_button: power-button {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pwr_key_l>;
36 debounce-interval = <100>;
[all …]
Dimx6q-logicpd.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include "imx6-logicpd-som.dtsi"
8 #include "imx6-logicpd-baseboard.dtsi"
11 model = "Logic PD i.MX6QD SOM-M3";
12 compatible = "logicpd,imx6q-logicpd", "fsl,imx6q";
14 backlight: backlight-lvds {
15 compatible = "pwm-backlight";
17 brightness-levels = <0 4 8 16 32 64 128 255>;
18 default-brightness-level = <6>;
[all …]
Dast2500-facebook-netbmc-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 #include "aspeed-g5.dtsi"
8 reg = <0x80000000 0x40000000>;
18 aspeed,reset-type = "system";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_txd1_default
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_txd3_default
48 m25p,fast-read;
54 m25p,fast-read;
[all …]
Dorion5x-lswsgl.dts3 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c,
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
48 #include <dt-bindings/gpio/gpio.h>
49 #include <dt-bindings/input/input.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include "orion5x-mv88f5182.dtsi"
54 model = "Buffalo Linkstation Mini (LS-WSGL)";
55 compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x";
[all …]
Dspear600.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
23 reg = <0 0x40000000>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
[all …]
Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
14 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
[all …]
Dkirkwood-goflexnet.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
13 reg = <0x00000000 0x8000000>;
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_usb_power_enable: pmx-usb-power-enable {
27 pmx_led_right_cap_0: pmx-led_right_cap_0 {
31 pmx_led_right_cap_1: pmx-led_right_cap_1 {
[all …]
Dkirkwood-blackarmor-nas220.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
13 #include "kirkwood-6192.dtsi"
17 compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
22 reg = <0x00000000 0x8000000>;
27 stdout-path = &uart0;
31 compatible = "gpio-poweroff";
[all …]
/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmmci.txt11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
[all …]
/linux-5.10/Documentation/devicetree/bindings/mtd/
Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
/linux-5.10/Documentation/devicetree/bindings/usb/
Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
16 - power : Should be "50". This signifies the controller can supply up to
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Damlogic,axg-spdifout.txt4 - compatible: 'amlogic,axg-spdifout' or
5 'amlogic,g12a-spdifout' or
6 'amlogic,sm1-spdifout'
7 - clocks: list of clock phandle, one for each entry clock-names.
8 - clock-names: should contain the following:
11 - #sound-dai-cells: must be 0.
14 - resets: phandle to the dedicated reset line of the spdif output.
18 spdifout: audio-controller@480 {
19 compatible = "amlogic,axg-spdifout";
20 reg = <0x0 0x480 0x0 0x50>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Dnuvoton,npcm-pspi.txt6 - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
7 - #address-cells : should be 1. see spi-bus.txt
8 - #size-cells : should be 0. see spi-bus.txt
9 - specifies physical base address and size of the register.
10 - interrupts : contain PSPI interrupt.
11 - clocks : phandle of PSPI reference clock.
12 - clock-names: Should be "clk_apb5".
13 - pinctrl-names : a pinctrl state named "default" must be defined.
14 - pinctrl-0 : phandle referencing pin configuration of the device.
15 - resets : phandle to the reset control for this device.
[all …]
/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-rock-pi-4c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3399-rock-pi-4.dtsi"
20 compatible = "brcm,bcm4329-fmac";
21 reg = <1>;
22 interrupt-parent = <&gpio0>;
24 interrupt-names = "host-wake";
25 pinctrl-names = "default";
26 pinctrl-0 = <&wifi_host_wake_l>;
34 compatible = "brcm,bcm43438-bt";
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxl-s905x-libretech-cc-v2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S905X-CC V2";
27 stdout-path = "serial0:115200n8";
[all …]
Dmeson-gxl-s805x-libretech-ac.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s805x.dtsi"
16 compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S805X-AC";
27 stdout-path = "serial0:115200n8";
30 cvbs-connector {
[all …]
/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a779a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a76";
[all …]
/linux-5.10/arch/arm64/boot/dts/cavium/
Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
/linux-5.10/drivers/gpio/
Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
51 const char names[4][3]; member
66 .names = { "A", "B", "C", "D" },
72 .names = { "E", "F", "G", "H" },
78 .names = { "I", "J" },
101 const enum aspeed_sgpio_reg reg) in bank_reg() argument
103 switch (reg) { in bank_reg()
105 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
107 return gpio->base + bank->rdata_reg; in bank_reg()
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dbrcm,bcmgenet.txt4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
32 - nvidia,tegra186-mc
[all …]
/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-s3c2410.txt6 - compatible: value should be either of the following.
7 (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
8 (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
9 (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
11 (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
13 - reg: physical base address of the controller and length of memory mapped
15 - interrupts: interrupt number to the cpu.
16 - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
18 Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
19 - Samsung GPIO variant (deprecated):
[all …]
/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
25 reg:
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-ufs.txt1 MediaTek Universal Flash Storage (UFS) M-PHY binding
2 --------------------------------------------------------
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
11 - compatible : Compatible list, contains the following controller:
12 "mediatek,mt8183-ufsphy" for ufs phy
14 - reg : Address and length of the UFS M-PHY register set.
[all …]

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