Home
last modified time | relevance | path

Searched +full:reg +full:- +full:names (Results 1851 – 1875 of 3549) sorted by relevance

1...<<71727374757677787980>>...142

/linux-5.10/Documentation/devicetree/bindings/usb/
Dmsm-hsusb.txt6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
14 reg = <0xf9a55000 0x400>;
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.txt9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
24 - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
30 - clocks:
34 - clock-indices:
37 - clock-output-names:
[all …]
Drockchip,rk3399-cru.txt9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
32 clock-output-names:
33 - "xin24m" - crystal input - required,
34 - "xin32k" - rtc clock - optional,
[all …]
Dbrcm,iproc-clocks.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
20 - reg:
24 - clocks:
28 - clock-output-names:
29 An ordered list of strings defining the names of the clocks
34 #clock-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
10 - Georgi Djakov <georgi.djakov@linaro.org>
11 - Odelu Kukatla <okukatla@codeaurora.org>
22 reg:
27 - qcom,sc7180-aggre1-noc
28 - qcom,sc7180-aggre2-noc
29 - qcom,sc7180-camnoc-virt
[all …]
/linux-5.10/arch/arm/boot/dts/
Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
18 reg = <0x40000000 0x80000000>;
22 stdout-path = "serial2:115200n8";
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
[all …]
Dat91-kizboxmini-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
5 * Copyright (C) 2014-2018 Overkiz SAS
16 stdout-path = &dbgu;
20 reg = <0x20000000 0x8000000>;
25 clock-frequency = <12000000>;
29 clock-frequency = <32768>;
38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
[all …]
Dat91-sama5d4_ma5d4evk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
7 #include "at91-sama5d4_ma5d4.dtsi"
14 stdout-path = "serial3:115200n8";
19 atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_usba_vbus>;
26 num-ports = <3>;
27 atmel,vbus-gpio = <0
42 hlcdc-display-controller {
[all …]
Dat91sam9x5ek.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
11 model = "Atmel AT91SAM9X5-EK";
16 stdout-path = "serial0:115200n8";
20 compatible = "atmel,sam9x5-wm8731-audio";
24 atmel,audio-routing =
30 atmel,ssc-controller = <&ssc0>;
31 atmel,audio-codec = <&wm8731>;
36 atmel,adc-ts-wires = <4>;
37 atmel,adc-ts-pressure-threshold = <10000>;
[all …]
Ddra76-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-evm-common.dtsi"
9 #include "dra76x-mmc-iodelay.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
25 reg = <0x0 0x80000000 0x0 0x80000000>;
28 reserved-memory {
29 #address-cells = <2>;
[all …]
Drk3036-kylin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
13 reg = <0x60000000 0x20000000>;
16 leds: gpio-leds {
17 compatible = "gpio-leds";
19 work_led: led-0 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&led_ctl>;
27 sdio_pwrseq: sdio-pwrseq {
[all …]
Dkirkwood-iomega_ix2_200.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
8 model = "Iomega StorCenter ix2-200";
9 compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
13 reg = <0x00000000 0x10000000>;
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
33 pinctrl-names = "default";
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-vega-s95.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gxbb.dtsi"
9 compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
17 stdout-path = "serial0:115200n8";
21 compatible = "gpio-leds";
23 led-blue {
24 label = "vega-s95:blue:on";
26 default-state = "on";
27 panic-indicator;
31 usb_pwr: regulator-usb-pwrs {
[all …]
/linux-5.10/arch/arm64/boot/dts/marvell/
Dcn9132-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9132-DB board.
8 #include "cn9131-db.dts"
11 model = "Marvell Armada CN9132-DB";
13 "marvell,armada-ap807-quad", "marvell,armada-ap807";
22 compatible = "regulator-fixed";
23 regulator-name = "cp2-xhci0-vbus";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 enable-active-high;
[all …]
/linux-5.10/arch/arc/boot/dts/
Dnsimosci.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
20 …8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
36 #clock-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt8183.txt6 - compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
12 - gpio-ranges : gpio valid number range.
13 - reg: physical address base for gpio base registers. There are 10 GPIO
17 - reg-names: gpio base register names. There are 10 gpio base register
18 names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
20 - interrupt-controller: Marks the device node as an interrupt controller
21 - #interrupt-cells: Should be two.
[all …]
/linux-5.10/drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/
Dsilabs,wfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jérôme Pouiller <jerome.pouiller@silabs.com>
24 In addition, it is recommended to declare a mmc-pwrseq on SDIO host above
25 WFx. Without it, you may encounter issues with warm boot. The mmc-pwrseq
26 should be compatible with mmc-pwrseq-simple. Please consult
27 Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml for more
33 Documentation/devicetree/bindings/spi/spi-controller.yaml for optional SPI
37 `mac-address` and `local-mac-address` as described in
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/omap/
Dl4.txt6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
14 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
15 Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
[all …]
/linux-5.10/Documentation/devicetree/bindings/pci/
Dhisilicon-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
20 - status: Either "ok" or "disabled".
21 - dma-coherent: Present if DMA operations are coherent.
25 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
26 reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dtda998x.txt1 Device-Tree bindings for the NXP TDA998x HDMI transmitter
4 - compatible: must be "nxp,tda998x"
6 - reg: I2C address
9 - port: Input port node with endpoint definition, as described
13 - interrupts: interrupt number and trigger type
16 - pinctrl-0: pin control group to be used for
19 - pinctrl-names: must contain a "default" entry.
21 - video-ports: 24 bits value which defines how the video controller
22 output is wired to the TDA998x input - default: <0x230145>
24 - audio-ports: array of 8-bit values, 2 values per one DAI[1].
[all …]
Dtoshiba,tc358767.txt4 - compatible: "toshiba,tc358767"
5 - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
6 - clock-names: should be "ref"
7 - clocks: OF device-tree clock specification for refclk input. The reference
11 - shutdown-gpios: OF device-tree gpio specification for SD pin
13 - reset-gpios: OF device-tree gpio specification for RSTX pin
15 - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
16 - ports: the ports node can contain video interface port nodes to connect
18 - port@0: DSI input port
19 - port@1: DPI input port
[all …]
/linux-5.10/Documentation/devicetree/bindings/gpio/
Dgpio-pca95xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - exar,xra1202
20 - maxim,max7310
21 - maxim,max7312
22 - maxim,max7313
23 - maxim,max7315
[all …]
/linux-5.10/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/linux-5.10/Documentation/devicetree/bindings/mtd/
Dmarvell-nand.txt4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
15 - #size-cells: shall be set to 0.
[all …]

1...<<71727374757677787980>>...142