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/linux-6.15/Documentation/devicetree/bindings/dma/
Dsprd,sc9860-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Orson Zhai <orsonzhai@gmail.com>
17 - Baolin Wang <baolin.wang7@gmail.com>
18 - Chunyan Zhang <zhang.lyra@gmail.com>
22 const: sprd,sc9860-dma
24 reg:
33 - description: DMA enable clock
[all …]
/linux-6.15/Documentation/devicetree/bindings/mmc/
Darm,pl18x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
[all …]
/linux-6.15/arch/arm/boot/dts/renesas/
Dr8a7740-armadillo800eva.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pwm/pwm.h>
25 stdout-path = "serial0:115200n8";
30 reg = <0x40000000 0x20000000>;
33 reg_3p3v: regulator-3p3v {
34 compatible = "regulator-fixed";
[all …]
/linux-6.15/Documentation/devicetree/bindings/iio/accel/
Dbosch,bma255.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Stephan Gerhold <stephan@gerhold.net>
15 4-wire interface.
20 # bmc150-accel driver in Linux
21 - bosch,bma222
22 - bosch,bma222e
23 - bosch,bma250e
[all …]
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt8186-corsola-krabby.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
17 remote-endpoint = <&ps8640_in>;
21 clock-frequency = <400000>;
23 edp-bridge@8 {
25 reg = <0x8>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&ps8640_pins>;
[all …]
/linux-6.15/Documentation/devicetree/bindings/clock/ti/davinci/
Dpsc.txt7 - compatible: shall be one of:
8 - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
15 - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
17 - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
[all …]
/linux-6.15/Documentation/devicetree/bindings/net/dsa/
Dqca,ar9331.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR9331 built-in switch
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and
14 addressable over internal MDIO bus. All PHYs are built-in as well.
18 const: qca,ar9331-switch
20 reg:
26 interrupt-controller: true
[all …]
Dbrcm,b53.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
18 - const: brcm,bcm5325
19 - const: brcm,bcm53101
20 - const: brcm,bcm53115
21 - const: brcm,bcm53125
22 - const: brcm,bcm53128
23 - const: brcm,bcm53134
[all …]
/linux-6.15/arch/arm/boot/dts/marvell/
Darmada-38x-solidrun-microsom.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/gpio/gpio.h>
13 reg = <0x00000000 0x10000000>; /* 256 MB */
23 internal-regs {
27 * twice in u-boot.
45 pinctrl-0 = <&ge0_rgmii_pins>;
46 pinctrl-names = "default";
48 phy-mode = "rgmii-id";
49 buffer-manager = <&bm>;
[all …]
/linux-6.15/arch/arm/boot/dts/aspeed/
Daspeed-bmc-tyan-s8036.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "tyan,s8036-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
19 reg = <0x80000000 0x20000000>;
22 reserved-memory {
23 #address-cells = <1>;
[all …]
Daspeed-bmc-lenovo-hr855xg2.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
35 reg = <0x80000000 0x20000000>;
38 reserved-memory {
39 #address-cells = <1>;
[all …]
/linux-6.15/arch/arm/boot/dts/microchip/
Dat91sam9x5cm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
11 reg = <0x20000000 0x8000000>;
16 clock-frequency = <32768>;
20 clock-frequency = <12000000>;
28 compatible = "atmel,tcb-timer";
29 reg = <0>;
33 compatible = "atmel,tcb-timer";
34 reg = <1>;
40 pinctrl_1wire_cm: 1wire_cm-0 {
[all …]
/linux-6.15/arch/arm64/boot/dts/qcom/
Dsc8280xp-huawei-gaokun3.dts1 // SPDX-License-Identifier: BSD-3-Clause
12 /dts-v1/;
14 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 #include <dt-bindings/phy/phy.h>
22 #include "sc8280xp-pmics.dtsi"
25 chassis-type = "tablet";
[all …]
/linux-6.15/Documentation/devicetree/bindings/timer/
Dfsl,ftm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,ftm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
14 const: fsl,ftm-timer
16 reg:
24 contain an entry for each entry in clock-names.
28 clock-names:
30 - const: ftm-evt
[all …]
/linux-6.15/Documentation/devicetree/bindings/clock/
Dloongson,ls2k-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Clock Control Module
10 - Yinbo Zhu <zhuyinbo@loongson.cn>
13 Loongson-2 SoC clock control module is an integrated clock controller, which
19 - loongson,ls2k0500-clk
20 - loongson,ls2k-clk # This is for Loongson-2K1000
21 - loongson,ls2k2000-clk
[all …]
/linux-6.15/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra30-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra124-i2s
18 - nvidia,tegra30-i2s
19 - items:
[all …]
Dqcom,lpass-wsa-macro.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-wsa-macro.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
15 - enum:
16 - qcom,sc7280-lpass-wsa-macro
17 - qcom,sm8250-lpass-wsa-macro
18 - qcom,sm8450-lpass-wsa-macro
19 - qcom,sm8550-lpass-wsa-macro
[all …]
/linux-6.15/Documentation/devicetree/bindings/serial/
Dmaxim,max310x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - maxim,max3107
16 - maxim,max3108
17 - maxim,max3109
18 - maxim,max14830
20 reg:
[all …]
Drenesas,em-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Magnus Damm <magnus.damm@gmail.com>
15 - items:
16 - enum:
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
20 - items:
[all …]
/linux-6.15/Documentation/devicetree/bindings/media/cec/
Dsamsung,s5p-cec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/cec/samsung,s5p-cec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
14 - $ref: cec-common.yaml#
18 const: samsung,s5p-cec
23 clock-names:
25 - const: hdmicec
[all …]
/linux-6.15/Documentation/devicetree/bindings/watchdog/
Dalphascale,asm9260-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/alphascale,asm9260-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <linux@rempel-privat.de>
13 - $ref: watchdog.yaml#
17 const: alphascale,asm9260-wdt
19 reg:
24 - description: source clock, used for tick counter
25 - description: ahb gate
[all …]
/linux-6.15/Documentation/devicetree/bindings/clock/ti/
Dadpll.txt4 register-mapped ADPLL with two to three selectable input clocks
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be one of "ti,dm814-adpll-s-clock" or
11 "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
12 - #clock-cells : from common clock binding; shall be set to 1.
13 - clocks : link phandles of parent clocks clkinp and clkinpulow, note
14 that the adpll-s-clock also has an optional clkinphif
15 - reg : address and length of the register set for controlling the ADPLL.
19 #clock-cells = <1>;
20 compatible = "ti,dm814-adpll-s-clock";
[all …]
/linux-6.15/arch/arm/boot/dts/allwinner/
Dsun7i-a20-lamobo-r1.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun7i-a20.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
52 compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
61 stdout-path = "serial0:115200n8";
64 hdmi-connector {
65 compatible = "hdmi-connector";
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^hdmi@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-hdmi
21 - nvidia,tegra30-hdmi
[all …]

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