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/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-axxia.txt4 - compatible : Must be "lsi,api2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - #address-cells : Must be <1>;
8 - #size-cells : Must be <0>;
9 - clock-names : Must contain "i2c".
10 - clocks: Must contain an entry for each name in clock-names. See the common
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
23 #address-cells = <1>;
24 #size-cells = <0>;
[all …]
Dnvidia,tegra20-i2c.txt4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Dmvebu-audio.txt5 - compatible:
6 "marvell,kirkwood-audio" for Kirkwood platforms
7 "marvell,dove-audio" for Dove platforms
8 "marvell,armada370-audio" for Armada 370 platforms
10 - reg: physical base address of the controller and length of memory mapped
13 - interrupts:
14 with "marvell,kirkwood-audio", the audio interrupt
15 with "marvell,dove-audio", a list of two interrupts, the first for
18 - clocks: one or two phandles.
22 - clock-names: names associated to the clocks:
[all …]
Dfsl,micfil.txt3 The MICFIL digital interface provides a 16-bit audio signal from a PDM
8 - compatible : Compatible list, contains "fsl,imx8mm-micfil"
10 - reg : Offset and length of the register set for the device.
12 - interrupts : Contains the micfil interrupts.
14 - clocks : Must contain an entry for each entry in clock-names.
16 - clock-names : Must include the "ipg_clk" for register access and
19 - dmas : Generic dma devicetree binding as described in
24 compatible = "fsl,imx8mm-micfil";
25 reg = <0x0 0x30080000 0x0 0x10000>;
30 clock-names = "ipg_clk", "ipg_clk_app";
Dfsl,esai.txt3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
15 "fsl,imx8qm-esai",
17 - reg : Offset and length of the register set for the device.
19 - interrupts : Contains the spdif interrupt.
21 - dmas : Generic dma devicetree binding as described in
24 - dma-names : Two dmas have to be defined, "tx" and "rx".
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/
Darm-pl08x.txt4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dralink,rt3050-esw.txt8 - compatible: Should be "ralink,rt3050-esw"
9 - reg: Address and length of the register set for the device
10 - interrupts: Should contain the embedded switches interrupt
11 - resets: Should contain the embedded switches resets
12 - reset-names: Should contain the reset names "esw"
15 - ralink,portmap: can be used to choose if the default switch setup is
17 - ralink,led_polarity: override the active high/low settings of the leds
22 compatible = "ralink,rt3050-esw";
23 reg = <0x10110000 8000>;
26 reset-names = "esw";
[all …]
/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.txt13 - name : Should be hsp
14 - compatible
17 - "nvidia,tegra186-hsp"
18 - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
19 - reg : Offset and length of the register set for the device.
20 - interrupt-names
22 Contains a list of names for the interrupts described by the interrupt
24 - "doorbell"
25 - "sharedN", where 'N' is a number from zero up to the number of
28 by name, using this interrupt-names property to do so.
[all …]
/linux-5.10/arch/arm/boot/dts/
Dimx6qdl-hummingboard.dtsi4 * This file is dual-licensed: you can use it either under the terms
41 #include <dt-bindings/sound/fsl-imx-audmux.h>
47 reg = <0x10000000 0>;
51 stdout-path = &uart1;
54 ir_recv: ir-receiver {
55 compatible = "gpio-ir-receiver";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
61 v_3v2: regulator-v-3v2 {
62 compatible = "regulator-fixed";
[all …]
Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
13 reg = <0x40000000 0x10000>;
15 #dma-channels = <32>;
16 #dma-cells = <2>;
17 #dma-requests = <75>;
21 pxairq: interrupt-controller@40d00000 {
22 marvell,intc-priority;
[all …]
Dr8a7745-iwg22d-sodimm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E SODIMM carrier board
9 * SSI-SGTL5000
31 /dts-v1/;
32 #include "r8a7745-iwg22m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
36 model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
47 stdout-path = "serial3:115200n8";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
[all …]
Dsun9i-a80-cubieboard4.dts5 * Chen-Yu Tsai <wens@csie.org>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun9i-a80.dtsi"
49 #include <dt-bindings/gpio/gpio.h>
53 compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80";
60 stdout-path = "serial0:115200n8";
64 compatible = "gpio-leds";
77 vga-connector {
78 compatible = "vga-connector";
[all …]
Dlogicpd-torpedo-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/input/input.h>
7 stdout-path = &uart1;
12 cpu0-supply = <&vcc>;
18 reg = <0x80000000 0>;
22 compatible = "gpio-leds";
26 linux,default-trigger = "none";
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <26000000>;
[all …]
Dimx27-apf27.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 compatible = "armadeus,imx27-apf27", "fsl,imx27";
18 reg = <0xa0000000 0x04000000>;
23 clock-frequency = <0>;
27 imx27-apf27 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_uart1>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_fec1>;
[all …]
Dmeson8b-mxq.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
22 stdout-path = "serial0:115200n8";
27 reg = <0x40000000 0x40000000>;
30 iio-hwmon {
31 compatible = "iio-hwmon";
32 io-channels = <&saradc 8>;
35 vcck: regulator-vcck {
36 compatible = "pwm-regulator";
[all …]
Dprima2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
[all …]
Ddm8148-t410.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
12 reg = <0x80000000 0x40000000>; /* 1 GB */
17 compatible = "regulator-fixed";
18 regulator-name = "usb_power";
19 regulator-min-microvolt = <5000000>;
20 regulator-max-microvolt = <5000000>;
22 enable-active-high;
23 regulator-always-on;
27 compatible = "regulator-fixed";
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Danalogix_dp.txt3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
16 -clock-names:
18 -phys:
[all …]
/linux-5.10/Documentation/devicetree/bindings/ufs/
Dufs-hisi.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
7 - compatible : compatible list, contains one of the following -
8 "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
10 "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
12 - reg : should contain UFS register address space & UFS SYS CTRL register address,
13 - interrupts : interrupt number
14 - clocks : List of phandle and clock specifier pairs
15 - clock-names : List of clock input name strings sorted in the same
17 - freq-table-hz : Array of <min max> operating frequencies stored in the same
22 - resets : describe reset node register
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dclk-s5pv210-audss.txt8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
19 - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
21 - sclk_audio0: Audio bus clock, parent of mout_i2s.
23 - clock-names: Aliases for the above clocks. They should be "hclk",
[all …]
/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a77951-salvator-xs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
5 * Copyright (C) 2015-2017 Renesas Electronics Corp.
8 /dts-v1/;
10 #include "salvator-xs.dtsi"
13 model = "Renesas Salvator-X 2nd version board based on r8a77951";
14 compatible = "renesas,salvator-xs", "renesas,r8a7795";
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
38 indicate this feature (arm,coresight-cti-v8-arch).
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
60 Note that some hardware trigger signals can be connected to non-CoreSight
64 - Mike Leach <mike.leach@linaro.org>
67 - $ref: /schemas/arm/primecell.yaml#
75 - arm,coresight-cti
[all …]
/linux-5.10/Documentation/devicetree/bindings/serial/
Drenesas,hscif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,hscif-r8a7778 # R-Car M1
21 - renesas,hscif-r8a7779 # R-Car H1
22 - const: renesas,rcar-gen1-hscif # R-Car Gen1
[all …]
/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
[all …]

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