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/linux-6.8/arch/arm/boot/dts/rockchip/
Drk3288-phycore-rdk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec PCM-947 carrier board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/leds-pca9532.h>
12 #include "rk3288-phycore-som.dtsi"
15 model = "Phytec RK3288 PCM-947";
16 compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
18 user_buttons: user-buttons {
19 compatible = "gpio-keys";
[all …]
/linux-6.8/arch/arm/boot/dts/marvell/
Darmada-xp-98dx3236.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
[all …]
/linux-6.8/arch/arm64/boot/dts/freescale/
Dimx93-tqma9352-mba93xxca.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
15 #include "imx93-tqma9352.dtsi"
18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";
[all …]
Dimx93-tqma9352.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
12 compatible = "tq,imx93-tqma9352", "fsl,imx93";
14 reserved-memory {
15 #address-cells = <2>;
16 #size-cells = <2>;
20 compatible = "shared-dma-pool";
22 alloc-ranges = <0 0x60000000 0 0x40000000>;
[all …]
/linux-6.8/arch/arm/boot/dts/ti/omap/
Domap3-beagle-xm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3";
15 cpu0-supply = <&vcc>;
21 reg = <0x80000000 0x20000000>; /* 512 MB */
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <26000000>;
37 led-controller-1 {
[all …]
Dam437x-cm-t43.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
6 /dts-v1/;
8 #include <dt-bindings/pinctrl/am43xx.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "CompuLab CM-T43";
15 compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
18 compatible = "gpio-leds";
21 label = "cm-t43:green";
[all …]
Domap3-beagle.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
11 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
15 cpu0-supply = <&vcc>;
21 reg = <0x80000000 0x10000000>; /* 256 MB */
30 compatible = "gpio-leds";
31 led-pmu-stat {
36 led-heartbeat {
38 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
[all …]
/linux-6.8/arch/arm/boot/dts/microchip/
Dat91-nattis-2-natte-2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
9 /dts-v1/;
10 #include "at91-linea.dtsi"
11 #include "at91-natte.dtsi"
14 model = "Axentia Linea-Nattis v2 Natte v2";
15 compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
18 gpio-keys {
19 compatible = "gpio-keys";
21 key-wakeup {
[all …]
/linux-6.8/arch/arm/boot/dts/nxp/imx/
Dimx50-kobo-aura.dts1 // SPDX-License-Identifier: GPL-2.0+
4 // The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
16 stdout-path = "serial1:115200n8";
21 reg = <0x70000000 0x10000000>;
24 gpio-leds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
[all …]
/linux-6.8/arch/arm/boot/dts/nxp/lpc/
Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
38 reg = <0x28000000 0x2000000>; /* 32 MB */
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
24 - mediatek,mt7622-snand
[all …]
Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
[all …]
/linux-6.8/arch/arm/boot/dts/st/
Dste-href-tvk1281618-r3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "gpio-keys";
13 #address-cells = <1>;
14 #size-cells = <0>;
15 vdd-supply = <&ab8500_ldo_aux1_reg>;
16 pinctrl-names = "default";
17 pinctrl-0 = <&hall_tvk_mode>;
31 reg = <0x44>;
[all …]
/linux-6.8/Documentation/devicetree/bindings/sound/
Dqcom,wcd934x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9340/WCD9341 Codec is a standalone Hi-Fi audio codec IC.
14 It has in-built Soundwire controller, pin controller, interrupt mux and
21 reg:
27 reset-gpios:
31 slim-ifc-dev:
38 clock-names:
[all …]
Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/linux-6.8/Documentation/devicetree/bindings/interconnect/
Dqcom,sdm660.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM660 Network-On-Chip interconnect
10 - Konrad Dybcio <konradybcio@kernel.org>
19 - qcom,sdm660-a2noc
20 - qcom,sdm660-bimc
21 - qcom,sdm660-cnoc
22 - qcom,sdm660-gnoc
23 - qcom,sdm660-mnoc
[all …]
/linux-6.8/arch/arm/boot/dts/renesas/
Dr8a7740-armadillo800eva.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pwm/pwm.h>
25 stdout-path = "serial0:115200n8";
30 reg = <0x40000000 0x20000000>;
33 reg_3p3v: regulator-3p3v {
34 compatible = "regulator-fixed";
[all …]
/linux-6.8/Documentation/devicetree/bindings/mmc/
Darm,pl18x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
[all …]
/linux-6.8/Documentation/devicetree/bindings/display/msm/
Dqcom,sm8350-dpu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Foss <robert.foss@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8350-dpu
18 reg:
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
[all …]
/linux-6.8/Documentation/devicetree/bindings/iio/accel/
Dbosch,bma255.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Stephan Gerhold <stephan@gerhold.net>
15 4-wire interface.
20 # bmc150-accel driver in Linux
21 - bosch,bma222
22 - bosch,bma222e
23 - bosch,bma250e
[all …]
/linux-6.8/Documentation/devicetree/bindings/clock/ti/davinci/
Dpsc.txt7 - compatible: shall be one of:
8 - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
15 - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
17 - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
[all …]
/linux-6.8/Documentation/devicetree/bindings/serial/
Dmaxim,max310x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART)
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
15 - maxim,max3107
16 - maxim,max3108
17 - maxim,max3109
18 - maxim,max14830
20 reg:
[all …]
Drenesas,em-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Magnus Damm <magnus.damm@gmail.com>
15 - items:
16 - enum:
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
20 - items:
[all …]
/linux-6.8/Documentation/devicetree/bindings/clock/
Dloongson,ls2k-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Clock Control Module
10 - Yinbo Zhu <zhuyinbo@loongson.cn>
13 Loongson-2 SoC clock control module is an integrated clock controller, which
19 - loongson,ls2k-clk
21 reg:
26 - description: 100m ref
[all …]

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