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/linux-6.15/Documentation/devicetree/bindings/timer/
Dsnps,dw-apb-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Lezcano <daniel.lezcano@linaro.org>
15 - const: snps,dw-apb-timer
16 - enum:
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
21 reg:
[all …]
/linux-6.15/Documentation/devicetree/bindings/ata/
Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
[all …]
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
27 reg = <0 0x40000000 0 0x40000000>;
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
[all …]
/linux-6.15/arch/arm/boot/dts/ti/omap/
Dam335x-bone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
9 cpu0-supply = <&dcdc2_reg>;
15 reg = <0x80000000 0x10000000>; /* 256 MB */
19 stdout-path = &uart0;
23 pinctrl-names = "default";
24 pinctrl-0 = <&user_leds_s0>;
26 compatible = "gpio-leds";
31 linux,default-trigger = "heartbeat";
32 default-state = "off";
[all …]
/linux-6.15/Documentation/devicetree/bindings/pci/
Drockchip-dw-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <cassel@kernel.org>
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
24 - rockchip,rk3568-pcie-ep
25 - rockchip,rk3588-pcie-ep
[all …]
/linux-6.15/arch/arm/boot/dts/nxp/imx/
Dimx6q-ba16.dtsi2 * Support for imx6 based Advantech DMS-BA16 Qseven module
7 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/gpio/gpio.h>
51 reg = <0x10000000 0x40000000>;
55 compatible = "pwm-backlight";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_display>;
59 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
85 default-brightness-level = <255>;
86 enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
[all …]
Dimx7d-nitrogen7.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
6 /dts-v1/;
12 compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
16 reg = <0x80000000 0x40000000>;
19 backlight-j9 {
20 compatible = "gpio-backlight";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_backlight_j9>;
24 default-on;
27 backlight_lcd: backlight-j20 {
[all …]
Dimx6qdl-apf6dev.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 stdout-path = &uart4;
15 compatible = "pwm-backlight";
17 brightness-levels = <0 4 8 16 32 64 128 255>;
18 default-brightness-level = <0>;
19 power-supply = <&reg_5v>;
23 compatible = "fsl,imx-parallel-display";
[all …]
Dimx6q-h100.dts4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
55 reg = <0x10000000 0>;
64 stdout-path = &uart2;
67 hdmi_osc: hdmi-osc {
68 compatible = "fixed-clock";
69 clock-output-names = "hdmi-osc";
70 clock-frequency = <27000000>;
[all …]
/linux-6.15/arch/arm64/boot/dts/arm/
Djuno-cs-r1r2.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
5 reg = <0 0x20130000 0 0x1000>;
8 clock-names = "apb_pclk";
9 power-domains = <&scpi_devpd 0>;
10 out-ports {
13 remote-endpoint = <&etf1_in_port>;
17 in-ports {
27 compatible = "arm,coresight-tmc", "arm,primecell";
28 reg = <0 0x20140000 0 0x1000>;
[all …]
/linux-6.15/arch/arm64/boot/dts/freescale/
Dimx95-19x19-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/usb/pd.h>
15 #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
16 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
17 #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
18 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
19 #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
23 compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
[all …]
/linux-6.15/Documentation/devicetree/bindings/remoteproc/
Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
31 - ti,am62a-c7xv-dsp
[all …]
/linux-6.15/Documentation/devicetree/bindings/net/
Dtoshiba,visconti-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
17 - toshiba,visconti-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
/linux-6.15/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
[all …]
/linux-6.15/Documentation/devicetree/bindings/fuse/
Dnvidia,tegra20-fuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-efuse
18 - nvidia,tegra30-efuse
19 - nvidia,tegra114-efuse
[all …]
/linux-6.15/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mq-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mq-vpu-blk-ctrl
22 reg:
25 '#power-domain-cells':
[all …]
/linux-6.15/Documentation/devicetree/bindings/ufs/
Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
19 reg:
25 clock-names:
27 - const: fck
[all …]
/linux-6.15/Documentation/devicetree/bindings/sound/
Dsocionext,uniphier-evea.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/socionext,uniphier-evea.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier EVEA SoC-internal sound codec
10 - <alsa-devel@alsa-project.org>
13 - $ref: dai-common.yaml#
17 const: socionext,uniphier-evea
19 reg:
22 clock-names:
[all …]
Dmicrochip,sama7g5-spdifrx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-spdifrx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
14 compliant with the IEC-60958 standard.
17 - $ref: dai-common.yaml#
20 "#sound-dai-cells":
24 const: microchip,sama7g5-spdifrx
26 reg:
[all …]
Dstarfive,jh7110-pwmdac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PWM-DAC Controller
10 The PWM-DAC Controller uses PWM square wave generators plus RC filters to
16 - Hal Feng <hal.feng@starfivetech.com>
19 - $ref: dai-common.yaml#
23 const: starfive,jh7110-pwmdac
25 reg:
[all …]
/linux-6.15/Documentation/devicetree/bindings/crypto/
Dstarfive,jh7110-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia Jie Ho <jiajie.ho@starfivetech.com>
11 - William Qiu <william.qiu@starfivetech.com>
16 - starfive,jh7110-crypto
17 - starfive,jh8100-crypto
19 reg:
24 - description: Hardware reference clock
[all …]
Datmel,at91sam9g46-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Tudor Ambarus <tudor.ambarus@linaro.org>
16 - const: atmel,at91sam9g46-aes
17 - items:
18 - const: microchip,sam9x7-aes
19 - const: atmel,at91sam9g46-aes
21 reg:
[all …]
/linux-6.15/arch/arm64/boot/dts/ti/
Dk3-am62-verdin-ivy.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
8 * https://www.toradex.com/products/carrier-board/ivy-carrier-board
11 #include <dt-bindings/mux/mux.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/net/ti-dp83867.h>
17 ain1_voltage_unmanaged: voltage-divider-ain1 {
18 compatible = "voltage-divider";
19 #io-channel-cells = <1>;
20 io-channels = <&ivy_adc1 0>;
[all …]
/linux-6.15/arch/arm/boot/dts/st/
Dstm32mp153c-lxa-tac-gen3.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
8 /dts-v1/;
11 #include "stm32mp15xc-lxa-tac.dtsi"
15 compatible = "lxa,stm32mp153c-tac-gen3", "oct,stm32mp153x-osd32", "st,stm32mp153";
18 compatible = "pwm-backlight";
19 power-supply = <&v3v3>;
21 brightness-levels = <0 31 63 95 127 159 191 223 255>;
22 default-brightness-level = <7>;
26 reg_iobus_12v: regulator-iobus-12v {
[all …]
/linux-6.15/arch/arm/boot/dts/microchip/
Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
22 reg = <0x70000000 0x4000000>;
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
43 compatible = "atmel,tcb-timer";
[all …]

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