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Searched +full:reg +full:- +full:mux (Results 1 – 9 of 9) sorted by relevance

/qemu/hw/misc/
H A Dstm32l4x5_rcc.c4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
41 * Function to simply acknowledge and propagate changes in a clock mux
46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) in clock_mux_update() argument
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H A Dtrace-events3 # allwinner-cpucfg.c
8 # allwinner-h3-dramc.c
18 # allwinner-r40-dramc.c
32 # allwinner-sid.c
36 # allwinner-sramc.c
45 axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
46 axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8
47 axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
101 # mps2-scc.c
108 # mps2-fpgaio.c
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H A Dzynq_slcr.c25 #include "hw/qdev-clock.h"
27 #include "hw/qdev-properties.h"
188 #define TYPE_ZYNQ_SLCR "xilinx-zynq_slcr"
229 /* frequency multiplier -> period division */ in zynq_slcr_compute_pll()
235 * + the periods in an array corresponding to input mux selector
242 * + bits[5:4] clock mux selector (index in array)
260 * "The 6-bit divider provides a divide range of 1 to 63" in zynq_slcr_compute_clock()
264 /* frequency divisor -> period multiplication */ in zynq_slcr_compute_clock()
272 #define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ argument
273 zynq_slcr_compute_clock((plls), (state)->regs[reg], \
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H A Dxlnx-versal-pmc-iou-slcr.c33 #include "hw/qdev-properties.h"
34 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
763 bool pending = s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR]; in parity_imr_update_irq()
764 qemu_set_irq(s->irq_parity_imr, pending); in parity_imr_update_irq()
767 static void parity_isr_postw(RegisterInfo *reg, uint64_t val64) in parity_isr_postw() argument
769 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_isr_postw()
773 static uint64_t parity_ier_prew(RegisterInfo *reg, uint64_t val64) in parity_ier_prew() argument
775 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_ier_prew()
778 s->regs[R_PARITY_IMR] &= ~val; in parity_ier_prew()
783 static uint64_t parity_idr_prew(RegisterInfo *reg, uint64_t val64) in parity_idr_prew() argument
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/qemu/include/hw/misc/
H A Dnpcm_clk.h31 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
45 /* SEL/MUX in CLK module. */
88 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
93 * @reg: The control registers for this PLL module.
103 int reg; member
107 * struct NPCM7xxClockSELState - A SEL module in CLK module.
130 * struct NPCM7xxClockDividerState - A Divider module in CLK module.
136 * @reg: The index of the control register that contains the divisor.
152 int reg; member
190 #define TYPE_NPCM_CLK "npcm-clk"
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/qemu/hw/i2c/
H A Dtrace-events4 bitbang_i2c_state(const char *old_state, const char *new_state) "state %s -> %s"
8 …c_data(unsigned clk, unsigned dat, unsigned old_out, unsigned new_out) "clk %u dat %u out %u -> %u"
20 smbus_ioport_readb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] -> val=0x%02x"
21 smbus_ioport_writeb(uint16_t addr, uint8_t data) "[0x%04" PRIx16 "] <- val=0x%02x"
26 …ead(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
27 …te(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
40 mpc_i2c_read(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] -> 0x%02" PRIx32
41 mpc_i2c_write(uint64_t addr, uint32_t value) "[0x%" PRIx64 "] <- 0x%02" PRIx32
55 # i2c-mux-pca954x.c
62 imx_i2c_read(const char *id, const char *reg, uint64_t ofs, uint64_t value) "%s:[%s (0x%" PRIx64 ")…
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/qemu/hw/arm/
H A Dxlnx-versal.c22 #include "hw/arm/xlnx-versal.h"
24 #include "target/arm/cpu-qom.h"
27 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
28 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
38 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, in versal_create_apu_cpus()
40 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); in versal_create_apu_cpus()
42 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { in versal_create_apu_cpus()
45 object_initialize_child(OBJECT(&s->fpd.apu.cluster), in versal_create_apu_cpus()
46 "apu-cpu[*]", &s->fpd.apu.cpu[i], in versal_create_apu_cpus()
48 obj = OBJECT(&s->fpd.apu.cpu[i]); in versal_create_apu_cpus()
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/qemu/linux-user/xtensa/
H A Dtermbits.h2 * include/asm-xtensa/termbits.h
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
305 #define TARGET_TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
321 #define TARGET_TIOCSERGETLSR _IOR('T', 89, unsigned int) /* Get line status reg. */
/qemu/hw/ssi/
H A Dxlnx-versal-ospi.c28 #include "hw/qdev-properties.h"
32 #include "hw/ssi/xlnx-versal-ospi.h"
323 #define IS_IND_DMA_START(op) (op->done_bytes == 0)
337 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_addr_len()
344 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_wr_data_len()
351 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_rd_data_len()
361 s->regs[R_IRQ_STATUS_REG] |= s->regs[R_IRQ_MASK_REG] & set_mask; in set_irq()
366 qemu_set_irq(s->irq, !!(s->regs[R_IRQ_STATUS_REG] & in ospi_update_irq_line()
367 s->regs[R_IRQ_MASK_REG])); in ospi_update_irq_line()
372 return ARRAY_FIELD_EX32(s->regs, in ospi_get_wr_opcode()
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