| /linux-5.10/arch/arm/mach-s3c/ |
| D | cpufreq-utils-s3c24xx.c | 23 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * Set the SDRAM refresh value appropriately for the configured
32 unsigned long refresh; in s3c2410_cpufreq_setrefresh() local
35 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2410_cpufreq_setrefresh()
38 * This should work for HCLK up to 133MHz and refresh period up in s3c2410_cpufreq_setrefresh()
42 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
43 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2410_cpufreq_setrefresh()
44 refresh = (1 << 11) + 1 - refresh; in s3c2410_cpufreq_setrefresh()
46 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); in s3c2410_cpufreq_setrefresh()
50 refval |= refresh; in s3c2410_cpufreq_setrefresh()
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| D | iotiming-s3c2412.c | 260 u32 refresh; in s3c2412_cpufreq_setrefresh() local
264 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2412_cpufreq_setrefresh()
267 * This should work for HCLK up to 133MHz and refresh period up in s3c2412_cpufreq_setrefresh()
271 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
272 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2412_cpufreq_setrefresh()
273 refresh &= ((1 << 16) - 1); in s3c2412_cpufreq_setrefresh()
275 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); in s3c2412_cpufreq_setrefresh()
277 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
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| /linux-5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
124 @ Clear self-refresh mode
131 @ Wait for EMC to clear self-refresh mode
135 bne 5b @ Branch until self-refresh has exited
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| D | pm.c | 40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
53 * Places DRAMs in self-refresh mode
128 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
129 * start of self-refresh. This only needs to be done once. in lpc32xx_pm_init()
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| /linux-5.10/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
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| D | s5pv210-cpufreq.c | 98 * DRAM configurations to calculate refresh counter for changing
103 unsigned long refresh; /* DRAM refresh counter * 1000 */ member
192 * This function set DRAM refresh counter
216 tmp1 = s5pv210_dram_conf[ch].refresh; in s5pv210_set_refresh()
273 * Reconfigure DRAM refresh counter value for minimum in s5pv210_target()
322 * 3. DMC1 refresh count for 133Mhz if (index == L4) is in s5pv210_target()
323 * true refresh counter is already programed in upper in s5pv210_target()
433 * 10. DMC1 refresh counter in s5pv210_target()
443 * and memory refresh parameter should be changed in s5pv210_target()
455 /* Reconfigure DRAM refresh counter value */ in s5pv210_target()
[all …]
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| /linux-5.10/drivers/video/fbdev/core/ |
| D | fbcvt.c | 38 u32 refresh; member
228 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
273 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
292 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
299 * @mode is filled with computed values. If interlaced, the refresh field
322 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
323 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
326 if (!cvt.xres || !cvt.yres || !cvt.refresh) { in fb_find_mode_cvt()
331 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
332 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
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| D | modedb.c | 549 mode->xres, mode->yres, bpp, mode->refresh); in fb_try_mode()
590 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][p][m]
594 * <name>[-<bpp>][@<refresh>]
596 * with <xres>, <yres>, <bpp> and <refresh> decimal numbers and
599 * If 'M' is present after yres (and before refresh/bpp if present),
613 * 2 if using specified @mode_option with an ignored refresh rate,
644 unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0; in fb_find_mode() local
656 refresh = simple_strtol(&name[i+1], NULL, in fb_find_mode()
723 (refresh) ? refresh : 60, in fb_find_mode()
731 cvt_mode.refresh = (refresh) ? refresh : 60; in fb_find_mode()
[all …]
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| /linux-5.10/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 27 * framework to implement panel self refresh (SR) support. Drivers are
32 * (meaning it knows how to initiate self refresh on the panel).
140 * update the average entry/exit self refresh times on self refresh transitions.
142 * entering self refresh mode after activity.
179 * incompatible with self refresh exit and changes them. This is a bit
181 * another. However in order to keep self refresh entirely hidden from
184 * At the end, we queue up the self refresh entry work so we can enter PSR after
227 * drm_self_refresh_helper_init - Initializes self refresh helpers for a crtc
228 * @crtc: the crtc which supports self refresh supported displays
265 * drm_self_refresh_helper_cleanup - Cleans up self refresh helpers for a crtc
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| /linux-5.10/arch/arm/mach-pxa/ |
| D | sleep.S | 54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
107 @ as possible to eliminate messing about with the refresh clock
159 @ external accesses after SDRAM is put in self-refresh mode
160 @ (see Errata 38 ...hangs when entering self-refresh mode)
165 @ put SDRAM into self-refresh
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| /linux-5.10/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
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| /linux-5.10/include/soc/at91/ |
| D | at91sam9_sdramc.h | 26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| D | at91sam9_ddrsdr.h | 21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
81 #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
82 #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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| /linux-5.10/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /linux-5.10/Documentation/fb/ |
| D | modedb.rst | 23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
30 <bpp> and <refresh>, if specified) the timings will be calculated using
81 and coordinated set of standard formats, display refresh rates, and
92 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
127 - acceptable refresh rates are 50, 60, 70 or 85 Hz only
128 - if reduced blanking, the refresh rate must be at 60Hz
152 video=<driver>:<xres>x<yres>[-<bpp>][@refresh]
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| /linux-5.10/arch/sh/boards/mach-ap325rxa/ |
| D | sdram.S | 3 * AP325RXA sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
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| /linux-5.10/arch/sh/boards/mach-migor/ |
| D | sdram.S | 3 * Migo-R sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
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| /linux-5.10/arch/sh/boards/mach-ecovec24/ |
| D | sdram.S | 3 * Ecovec24 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-driver-hid-picolcd | 31 Description: Make it possible to adjust defio refresh rate.
33 Reading: returns list of available refresh rates (expressed in Hz),
34 the active refresh rate being enclosed in brackets ('[' and ']')
36 Writing: accepts new refresh rate expressed in integer Hz
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| /linux-5.10/arch/sh/boards/mach-se/7724/ |
| D | sdram.S | 3 * MS7724SE sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
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| /linux-5.10/drivers/gpu/drm/amd/display/modules/freesync/ |
| D | freesync.c | 36 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
44 /*Threshold to exit fixed refresh rate*/
46 /* Number of consecutive frames to check before entering/exiting fixed refresh*/
200 * standard frame duration (frame duration at 60 Hz refresh rate). in update_v_total_for_static_ramp()
205 /* Going to a higher refresh rate (lower frame duration) */ in update_v_total_for_static_ramp()
218 /* Going to a lower refresh rate (larger frame duration) */ in update_v_total_for_static_ramp()
406 /* Compute the exit refresh rate and exit frame duration */ in apply_fixed_refresh()
412 /* Exit Fixed Refresh mode */ in apply_fixed_refresh()
425 /* Enter Fixed Refresh mode */ in apply_fixed_refresh()
549 /* PB7 = FreeSync Minimum refresh rate (Hz) */ in build_vrr_infopacket_data_v1()
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 38 self-refresh idle period in which memories are
39 placed into self-refresh mode if bus is idle
44 - rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
46 into self-refresh mode and memory controller
50 - rockchip,srpd_lite_idle : Defines the self-refresh power down idle
52 self-refresh power down mode if bus is idle
57 memories are placed into self-refresh mode.
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| /linux-5.10/arch/sh/kernel/cpu/shmobile/ |
| D | pm.c | 28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
107 /* part 2: board specific code to enter self-refresh mode */ in sh_mobile_register_self_refresh()
113 /* part 3: board specific code to resume from self-refresh mode */ in sh_mobile_register_self_refresh()
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| /linux-5.10/arch/arm/mach-at91/ |
| D | pm_suspend.S | 111 /* Active the self-refresh mode */
135 /* Exit the self-refresh mode */
556 * @r0: 1 - active self-refresh mode
557 * 0 - exit self-refresh mode
575 * For exiting the self-refresh mode, do nothing,
576 * automatically exit the self-refresh mode.
581 /* Active SDRAM self-refresh mode */
596 /* LPDDR1 --> force DDR2 mode during self-refresh */
606 /* Active DDRC self-refresh mode */
627 /* Active DDRC self-refresh mode */
[all …]
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