1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/reset/imx8mp-reset-audiomix.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interconnect/fsl,imx8mp.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/thermal/thermal.h> 15 16#include "imx8mp-pinfunc.h" 17 18/ { 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec; 25 ethernet1 = &eqos; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 i2c3 = &i2c4; 35 i2c4 = &i2c5; 36 i2c5 = &i2c6; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 serial0 = &uart1; 41 serial1 = &uart2; 42 serial2 = &uart3; 43 serial3 = &uart4; 44 spi0 = &flexspi; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 idle-states { 52 entry-method = "psci"; 53 54 cpu_pd_wait: cpu-pd-wait { 55 compatible = "arm,idle-state"; 56 arm,psci-suspend-param = <0x0010033>; 57 local-timer-stop; 58 entry-latency-us = <1000>; 59 exit-latency-us = <700>; 60 min-residency-us = <2700>; 61 wakeup-latency-us = <1500>; 62 }; 63 }; 64 65 A53_0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x0>; 69 clocks = <&clk IMX8MP_CLK_ARM>; 70 enable-method = "psci"; 71 i-cache-size = <0x8000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&A53_L2>; 78 nvmem-cells = <&cpu_speed_grade>; 79 nvmem-cell-names = "speed_grade"; 80 operating-points-v2 = <&a53_opp_table>; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 }; 84 85 A53_1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x1>; 89 clocks = <&clk IMX8MP_CLK_ARM>; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&A53_L2>; 98 operating-points-v2 = <&a53_opp_table>; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 }; 102 103 A53_2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x2>; 107 clocks = <&clk IMX8MP_CLK_ARM>; 108 enable-method = "psci"; 109 i-cache-size = <0x8000>; 110 i-cache-line-size = <64>; 111 i-cache-sets = <256>; 112 d-cache-size = <0x8000>; 113 d-cache-line-size = <64>; 114 d-cache-sets = <128>; 115 next-level-cache = <&A53_L2>; 116 operating-points-v2 = <&a53_opp_table>; 117 #cooling-cells = <2>; 118 cpu-idle-states = <&cpu_pd_wait>; 119 }; 120 121 A53_3: cpu@3 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x3>; 125 clocks = <&clk IMX8MP_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 #cooling-cells = <2>; 136 cpu-idle-states = <&cpu_pd_wait>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-unified; 142 cache-level = <2>; 143 cache-size = <0x80000>; 144 cache-line-size = <64>; 145 cache-sets = <512>; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0x8a0>, <0x7>; 157 clock-latency-ns = <150000>; 158 opp-suspend; 159 }; 160 161 opp-1600000000 { 162 opp-hz = /bits/ 64 <1600000000>; 163 opp-microvolt = <950000>; 164 opp-supported-hw = <0xa0>, <0x7>; 165 clock-latency-ns = <150000>; 166 opp-suspend; 167 }; 168 169 opp-1800000000 { 170 opp-hz = /bits/ 64 <1800000000>; 171 opp-microvolt = <1000000>; 172 opp-supported-hw = <0x20>, <0x3>; 173 clock-latency-ns = <150000>; 174 opp-suspend; 175 }; 176 }; 177 178 osc_32k: clock-osc-32k { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <32768>; 182 clock-output-names = "osc_32k"; 183 }; 184 185 osc_24m: clock-osc-24m { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc_24m"; 190 }; 191 192 clk_ext1: clock-ext1 { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <133000000>; 196 clock-output-names = "clk_ext1"; 197 }; 198 199 clk_ext2: clock-ext2 { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <133000000>; 203 clock-output-names = "clk_ext2"; 204 }; 205 206 clk_ext3: clock-ext3 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <133000000>; 210 clock-output-names = "clk_ext3"; 211 }; 212 213 clk_ext4: clock-ext4 { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <133000000>; 217 clock-output-names = "clk_ext4"; 218 }; 219 220 funnel { 221 /* 222 * non-configurable funnel don't show up on the AMBA 223 * bus. As such no need to add "arm,primecell". 224 */ 225 compatible = "arm,coresight-static-funnel"; 226 227 in-ports { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 port@0 { 232 reg = <0>; 233 234 ca_funnel_in_port0: endpoint { 235 remote-endpoint = <&etm0_out_port>; 236 }; 237 }; 238 239 port@1 { 240 reg = <1>; 241 242 ca_funnel_in_port1: endpoint { 243 remote-endpoint = <&etm1_out_port>; 244 }; 245 }; 246 247 port@2 { 248 reg = <2>; 249 250 ca_funnel_in_port2: endpoint { 251 remote-endpoint = <&etm2_out_port>; 252 }; 253 }; 254 255 port@3 { 256 reg = <3>; 257 258 ca_funnel_in_port3: endpoint { 259 remote-endpoint = <&etm3_out_port>; 260 }; 261 }; 262 }; 263 264 out-ports { 265 port { 266 267 ca_funnel_out_port0: endpoint { 268 remote-endpoint = <&hugo_funnel_in_port0>; 269 }; 270 }; 271 }; 272 }; 273 274 reserved-memory { 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 279 dsp_reserved: dsp@92400000 { 280 reg = <0 0x92400000 0 0x1000000>; 281 no-map; 282 status = "disabled"; 283 }; 284 }; 285 286 pmu { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts = <GIC_PPI 7 289 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 290 }; 291 292 psci { 293 compatible = "arm,psci-1.0"; 294 method = "smc"; 295 }; 296 297 thermal-zones { 298 cpu-thermal { 299 polling-delay-passive = <250>; 300 polling-delay = <2000>; 301 thermal-sensors = <&tmu 0>; 302 trips { 303 cpu_alert0: trip0 { 304 temperature = <85000>; 305 hysteresis = <2000>; 306 type = "passive"; 307 }; 308 309 cpu_crit0: trip1 { 310 temperature = <95000>; 311 hysteresis = <2000>; 312 type = "critical"; 313 }; 314 }; 315 316 cooling-maps { 317 map0 { 318 trip = <&cpu_alert0>; 319 cooling-device = 320 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 321 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 322 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 323 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 324 <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 325 <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 326 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 327 }; 328 }; 329 }; 330 331 soc-thermal { 332 polling-delay-passive = <250>; 333 polling-delay = <2000>; 334 thermal-sensors = <&tmu 1>; 335 trips { 336 soc_alert0: trip0 { 337 temperature = <85000>; 338 hysteresis = <2000>; 339 type = "passive"; 340 }; 341 342 soc_crit0: trip1 { 343 temperature = <95000>; 344 hysteresis = <2000>; 345 type = "critical"; 346 }; 347 }; 348 349 cooling-maps { 350 map0 { 351 trip = <&soc_alert0>; 352 cooling-device = 353 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 354 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 357 <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 358 <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 359 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 360 }; 361 }; 362 }; 363 }; 364 365 timer { 366 compatible = "arm,armv8-timer"; 367 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 368 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 369 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 370 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 371 clock-frequency = <8000000>; 372 arm,no-tick-in-suspend; 373 }; 374 375 soc: soc@0 { 376 compatible = "fsl,imx8mp-soc", "simple-bus"; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 ranges = <0x0 0x0 0x0 0x3e000000>; 380 nvmem-cells = <&imx8mp_uid>; 381 nvmem-cell-names = "soc_unique_id"; 382 383 etm0: etm@28440000 { 384 compatible = "arm,coresight-etm4x", "arm,primecell"; 385 reg = <0x28440000 0x1000>; 386 cpu = <&A53_0>; 387 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 388 clock-names = "apb_pclk"; 389 390 out-ports { 391 port { 392 etm0_out_port: endpoint { 393 remote-endpoint = <&ca_funnel_in_port0>; 394 }; 395 }; 396 }; 397 }; 398 399 etm1: etm@28540000 { 400 compatible = "arm,coresight-etm4x", "arm,primecell"; 401 reg = <0x28540000 0x1000>; 402 cpu = <&A53_1>; 403 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 404 clock-names = "apb_pclk"; 405 406 out-ports { 407 port { 408 etm1_out_port: endpoint { 409 remote-endpoint = <&ca_funnel_in_port1>; 410 }; 411 }; 412 }; 413 }; 414 415 etm2: etm@28640000 { 416 compatible = "arm,coresight-etm4x", "arm,primecell"; 417 reg = <0x28640000 0x1000>; 418 cpu = <&A53_2>; 419 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 420 clock-names = "apb_pclk"; 421 422 out-ports { 423 port { 424 etm2_out_port: endpoint { 425 remote-endpoint = <&ca_funnel_in_port2>; 426 }; 427 }; 428 }; 429 }; 430 431 etm3: etm@28740000 { 432 compatible = "arm,coresight-etm4x", "arm,primecell"; 433 reg = <0x28740000 0x1000>; 434 cpu = <&A53_3>; 435 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 436 clock-names = "apb_pclk"; 437 438 out-ports { 439 port { 440 etm3_out_port: endpoint { 441 remote-endpoint = <&ca_funnel_in_port3>; 442 }; 443 }; 444 }; 445 }; 446 447 funnel@28c03000 { 448 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 449 reg = <0x28c03000 0x1000>; 450 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 451 clock-names = "apb_pclk"; 452 453 in-ports { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 port@0 { 458 reg = <0>; 459 460 hugo_funnel_in_port0: endpoint { 461 remote-endpoint = <&ca_funnel_out_port0>; 462 }; 463 }; 464 465 port@1 { 466 reg = <1>; 467 468 hugo_funnel_in_port1: endpoint { 469 /* M7 input */ 470 }; 471 }; 472 473 port@2 { 474 reg = <2>; 475 476 hugo_funnel_in_port2: endpoint { 477 /* DSP input */ 478 }; 479 }; 480 /* the other input ports are not connect to anything */ 481 }; 482 483 out-ports { 484 port { 485 hugo_funnel_out_port0: endpoint { 486 remote-endpoint = <&etf_in_port>; 487 }; 488 }; 489 }; 490 }; 491 492 etf@28c04000 { 493 compatible = "arm,coresight-tmc", "arm,primecell"; 494 reg = <0x28c04000 0x1000>; 495 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 496 clock-names = "apb_pclk"; 497 498 in-ports { 499 port { 500 etf_in_port: endpoint { 501 remote-endpoint = <&hugo_funnel_out_port0>; 502 }; 503 }; 504 }; 505 506 out-ports { 507 port { 508 etf_out_port: endpoint { 509 remote-endpoint = <&etr_in_port>; 510 }; 511 }; 512 }; 513 }; 514 515 etr@28c06000 { 516 compatible = "arm,coresight-tmc", "arm,primecell"; 517 reg = <0x28c06000 0x1000>; 518 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 519 clock-names = "apb_pclk"; 520 521 in-ports { 522 port { 523 etr_in_port: endpoint { 524 remote-endpoint = <&etf_out_port>; 525 }; 526 }; 527 }; 528 }; 529 530 aips1: bus@30000000 { 531 compatible = "fsl,aips-bus", "simple-bus"; 532 reg = <0x30000000 0x400000>; 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges; 536 537 gpio1: gpio@30200000 { 538 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 539 reg = <0x30200000 0x10000>; 540 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 gpio-ranges = <&iomuxc 0 5 30>; 548 }; 549 550 gpio2: gpio@30210000 { 551 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 552 reg = <0x30210000 0x10000>; 553 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 gpio-ranges = <&iomuxc 0 35 21>; 561 }; 562 563 gpio3: gpio@30220000 { 564 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 565 reg = <0x30220000 0x10000>; 566 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 574 }; 575 576 gpio4: gpio@30230000 { 577 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 578 reg = <0x30230000 0x10000>; 579 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 582 gpio-controller; 583 #gpio-cells = <2>; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 gpio-ranges = <&iomuxc 0 82 32>; 587 }; 588 589 gpio5: gpio@30240000 { 590 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 591 reg = <0x30240000 0x10000>; 592 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 gpio-ranges = <&iomuxc 0 114 30>; 600 }; 601 602 tmu: tmu@30260000 { 603 compatible = "fsl,imx8mp-tmu"; 604 reg = <0x30260000 0x10000>; 605 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 606 nvmem-cells = <&tmu_calib>; 607 nvmem-cell-names = "calib"; 608 #thermal-sensor-cells = <1>; 609 }; 610 611 wdog1: watchdog@30280000 { 612 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 613 reg = <0x30280000 0x10000>; 614 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 616 status = "disabled"; 617 }; 618 619 wdog2: watchdog@30290000 { 620 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 621 reg = <0x30290000 0x10000>; 622 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 624 status = "disabled"; 625 }; 626 627 wdog3: watchdog@302a0000 { 628 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 629 reg = <0x302a0000 0x10000>; 630 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 632 status = "disabled"; 633 }; 634 635 gpt1: timer@302d0000 { 636 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 637 reg = <0x302d0000 0x10000>; 638 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 640 clock-names = "ipg", "per"; 641 }; 642 643 gpt2: timer@302e0000 { 644 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 645 reg = <0x302e0000 0x10000>; 646 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 648 clock-names = "ipg", "per"; 649 }; 650 651 gpt3: timer@302f0000 { 652 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 653 reg = <0x302f0000 0x10000>; 654 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 656 clock-names = "ipg", "per"; 657 }; 658 659 iomuxc: pinctrl@30330000 { 660 compatible = "fsl,imx8mp-iomuxc"; 661 reg = <0x30330000 0x10000>; 662 }; 663 664 gpr: syscon@30340000 { 665 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 666 reg = <0x30340000 0x10000>; 667 }; 668 669 ocotp: efuse@30350000 { 670 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 671 reg = <0x30350000 0x10000>; 672 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 673 /* For nvmem subnodes */ 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 /* 678 * The register address below maps to the MX8M 679 * Fusemap Description Table entries this way. 680 * Assuming 681 * reg = <ADDR SIZE>; 682 * then 683 * Fuse Address = (ADDR * 4) + 0x400 684 * Note that if SIZE is greater than 4, then 685 * each subsequent fuse is located at offset 686 * +0x10 in Fusemap Description Table (e.g. 687 * reg = <0x8 0x8> describes fuses 0x420 and 688 * 0x430). 689 */ 690 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 691 reg = <0x8 0x8>; 692 }; 693 694 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 695 reg = <0x10 4>; 696 }; 697 698 eth_mac1: mac-address@90 { /* 0x640 */ 699 reg = <0x90 6>; 700 }; 701 702 eth_mac2: mac-address@96 { /* 0x658 */ 703 reg = <0x96 6>; 704 }; 705 706 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 707 reg = <0x264 0x10>; 708 }; 709 }; 710 711 anatop: clock-controller@30360000 { 712 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 713 reg = <0x30360000 0x10000>; 714 #clock-cells = <1>; 715 }; 716 717 snvs: snvs@30370000 { 718 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 719 reg = <0x30370000 0x10000>; 720 721 snvs_rtc: snvs-rtc-lp { 722 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 723 regmap = <&snvs>; 724 offset = <0x34>; 725 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 728 clock-names = "snvs-rtc"; 729 }; 730 731 snvs_pwrkey: snvs-powerkey { 732 compatible = "fsl,sec-v4.0-pwrkey"; 733 regmap = <&snvs>; 734 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 736 clock-names = "snvs-pwrkey"; 737 linux,keycode = <KEY_POWER>; 738 wakeup-source; 739 status = "disabled"; 740 }; 741 742 snvs_lpgpr: snvs-lpgpr { 743 compatible = "fsl,imx8mp-snvs-lpgpr", 744 "fsl,imx7d-snvs-lpgpr"; 745 }; 746 }; 747 748 clk: clock-controller@30380000 { 749 compatible = "fsl,imx8mp-ccm"; 750 reg = <0x30380000 0x10000>; 751 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 753 #clock-cells = <1>; 754 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 755 <&clk_ext3>, <&clk_ext4>; 756 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 757 "clk_ext3", "clk_ext4"; 758 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 759 <&clk IMX8MP_CLK_A53_CORE>, 760 <&clk IMX8MP_CLK_NOC>, 761 <&clk IMX8MP_CLK_NOC_IO>, 762 <&clk IMX8MP_CLK_GIC>; 763 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 764 <&clk IMX8MP_ARM_PLL_OUT>, 765 <&clk IMX8MP_SYS_PLL2_1000M>, 766 <&clk IMX8MP_SYS_PLL1_800M>, 767 <&clk IMX8MP_SYS_PLL2_500M>; 768 assigned-clock-rates = <0>, <0>, 769 <1000000000>, 770 <800000000>, 771 <500000000>; 772 }; 773 774 src: reset-controller@30390000 { 775 compatible = "fsl,imx8mp-src", "syscon"; 776 reg = <0x30390000 0x10000>; 777 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 778 #reset-cells = <1>; 779 }; 780 781 gpc: gpc@303a0000 { 782 compatible = "fsl,imx8mp-gpc"; 783 reg = <0x303a0000 0x1000>; 784 interrupt-parent = <&gic>; 785 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-controller; 787 #interrupt-cells = <3>; 788 789 pgc { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 793 pgc_mipi_phy1: power-domain@0 { 794 #power-domain-cells = <0>; 795 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 796 }; 797 798 pgc_pcie_phy: power-domain@1 { 799 #power-domain-cells = <0>; 800 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 801 }; 802 803 pgc_usb1_phy: power-domain@2 { 804 #power-domain-cells = <0>; 805 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 806 }; 807 808 pgc_usb2_phy: power-domain@3 { 809 #power-domain-cells = <0>; 810 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 811 }; 812 813 pgc_mlmix: power-domain@4 { 814 #power-domain-cells = <0>; 815 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 816 clocks = <&clk IMX8MP_CLK_ML_AXI>, 817 <&clk IMX8MP_CLK_ML_AHB>, 818 <&clk IMX8MP_CLK_NPU_ROOT>; 819 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 820 <&clk IMX8MP_CLK_ML_AXI>, 821 <&clk IMX8MP_CLK_ML_AHB>; 822 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 823 <&clk IMX8MP_SYS_PLL1_800M>, 824 <&clk IMX8MP_SYS_PLL1_800M>; 825 assigned-clock-rates = <1000000000>, 826 <800000000>, 827 <400000000>; 828 }; 829 830 pgc_audio: power-domain@5 { 831 #power-domain-cells = <0>; 832 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 833 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 834 <&clk IMX8MP_CLK_AUDIO_AXI>; 835 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 836 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 837 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 838 <&clk IMX8MP_SYS_PLL1_800M>; 839 assigned-clock-rates = <400000000>, 840 <800000000>; 841 }; 842 843 pgc_gpu2d: power-domain@6 { 844 #power-domain-cells = <0>; 845 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 846 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 847 power-domains = <&pgc_gpumix>; 848 }; 849 850 pgc_gpumix: power-domain@7 { 851 #power-domain-cells = <0>; 852 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 853 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 854 <&clk IMX8MP_CLK_GPU_AHB>; 855 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 856 <&clk IMX8MP_CLK_GPU_AHB>; 857 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 858 <&clk IMX8MP_SYS_PLL1_800M>; 859 assigned-clock-rates = <800000000>, <400000000>; 860 }; 861 862 pgc_vpumix: power-domain@8 { 863 #power-domain-cells = <0>; 864 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 865 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 866 }; 867 868 pgc_gpu3d: power-domain@9 { 869 #power-domain-cells = <0>; 870 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 871 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 872 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 873 power-domains = <&pgc_gpumix>; 874 }; 875 876 pgc_mediamix: power-domain@10 { 877 #power-domain-cells = <0>; 878 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 879 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 880 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 881 }; 882 883 pgc_vpu_g1: power-domain@11 { 884 #power-domain-cells = <0>; 885 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 886 }; 887 888 pgc_vpu_g2: power-domain@12 { 889 #power-domain-cells = <0>; 890 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 891 }; 892 893 pgc_vpu_vc8000e: power-domain@13 { 894 #power-domain-cells = <0>; 895 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 896 }; 897 898 pgc_hdmimix: power-domain@14 { 899 #power-domain-cells = <0>; 900 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 901 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 902 <&clk IMX8MP_CLK_HDMI_APB>; 903 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 904 <&clk IMX8MP_CLK_HDMI_APB>; 905 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 906 <&clk IMX8MP_SYS_PLL1_133M>; 907 assigned-clock-rates = <500000000>, <133000000>; 908 }; 909 910 pgc_hdmi_phy: power-domain@15 { 911 #power-domain-cells = <0>; 912 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 913 }; 914 915 pgc_mipi_phy2: power-domain@16 { 916 #power-domain-cells = <0>; 917 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 918 }; 919 920 pgc_hsiomix: power-domain@17 { 921 #power-domain-cells = <0>; 922 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 923 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 924 <&clk IMX8MP_CLK_HSIO_ROOT>; 925 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 926 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 927 assigned-clock-rates = <500000000>; 928 }; 929 930 pgc_ispdwp: power-domain@18 { 931 #power-domain-cells = <0>; 932 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 933 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 934 }; 935 }; 936 }; 937 }; 938 939 aips2: bus@30400000 { 940 compatible = "fsl,aips-bus", "simple-bus"; 941 reg = <0x30400000 0x400000>; 942 #address-cells = <1>; 943 #size-cells = <1>; 944 ranges; 945 946 pwm1: pwm@30660000 { 947 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 948 reg = <0x30660000 0x10000>; 949 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 951 <&clk IMX8MP_CLK_PWM1_ROOT>; 952 clock-names = "ipg", "per"; 953 #pwm-cells = <3>; 954 status = "disabled"; 955 }; 956 957 pwm2: pwm@30670000 { 958 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 959 reg = <0x30670000 0x10000>; 960 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 962 <&clk IMX8MP_CLK_PWM2_ROOT>; 963 clock-names = "ipg", "per"; 964 #pwm-cells = <3>; 965 status = "disabled"; 966 }; 967 968 pwm3: pwm@30680000 { 969 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 970 reg = <0x30680000 0x10000>; 971 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 973 <&clk IMX8MP_CLK_PWM3_ROOT>; 974 clock-names = "ipg", "per"; 975 #pwm-cells = <3>; 976 status = "disabled"; 977 }; 978 979 pwm4: pwm@30690000 { 980 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 981 reg = <0x30690000 0x10000>; 982 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 984 <&clk IMX8MP_CLK_PWM4_ROOT>; 985 clock-names = "ipg", "per"; 986 #pwm-cells = <3>; 987 status = "disabled"; 988 }; 989 990 system_counter: timer@306a0000 { 991 compatible = "nxp,sysctr-timer"; 992 reg = <0x306a0000 0x20000>; 993 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&osc_24m>; 995 clock-names = "per"; 996 }; 997 998 gpt6: timer@306e0000 { 999 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1000 reg = <0x306e0000 0x10000>; 1001 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 1003 clock-names = "ipg", "per"; 1004 }; 1005 1006 gpt5: timer@306f0000 { 1007 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1008 reg = <0x306f0000 0x10000>; 1009 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 1011 clock-names = "ipg", "per"; 1012 }; 1013 1014 gpt4: timer@30700000 { 1015 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1016 reg = <0x30700000 0x10000>; 1017 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1019 clock-names = "ipg", "per"; 1020 }; 1021 }; 1022 1023 aips3: bus@30800000 { 1024 compatible = "fsl,aips-bus", "simple-bus"; 1025 reg = <0x30800000 0x400000>; 1026 #address-cells = <1>; 1027 #size-cells = <1>; 1028 ranges; 1029 1030 spba-bus@30800000 { 1031 compatible = "fsl,spba-bus", "simple-bus"; 1032 reg = <0x30800000 0x100000>; 1033 #address-cells = <1>; 1034 #size-cells = <1>; 1035 ranges; 1036 1037 ecspi1: spi@30820000 { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1041 reg = <0x30820000 0x10000>; 1042 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1044 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1045 clock-names = "ipg", "per"; 1046 assigned-clock-rates = <80000000>; 1047 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1048 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1049 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1050 dma-names = "rx", "tx"; 1051 status = "disabled"; 1052 }; 1053 1054 ecspi2: spi@30830000 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1058 reg = <0x30830000 0x10000>; 1059 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1061 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1062 clock-names = "ipg", "per"; 1063 assigned-clock-rates = <80000000>; 1064 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1065 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1066 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1067 dma-names = "rx", "tx"; 1068 status = "disabled"; 1069 }; 1070 1071 ecspi3: spi@30840000 { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1075 reg = <0x30840000 0x10000>; 1076 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1078 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1079 clock-names = "ipg", "per"; 1080 assigned-clock-rates = <80000000>; 1081 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1082 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1083 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1084 dma-names = "rx", "tx"; 1085 status = "disabled"; 1086 }; 1087 1088 uart1: serial@30860000 { 1089 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1090 reg = <0x30860000 0x10000>; 1091 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1093 <&clk IMX8MP_CLK_UART1_ROOT>; 1094 clock-names = "ipg", "per"; 1095 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1096 dma-names = "rx", "tx"; 1097 status = "disabled"; 1098 }; 1099 1100 uart3: serial@30880000 { 1101 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1102 reg = <0x30880000 0x10000>; 1103 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1105 <&clk IMX8MP_CLK_UART3_ROOT>; 1106 clock-names = "ipg", "per"; 1107 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1108 dma-names = "rx", "tx"; 1109 status = "disabled"; 1110 }; 1111 1112 uart2: serial@30890000 { 1113 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1114 reg = <0x30890000 0x10000>; 1115 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1117 <&clk IMX8MP_CLK_UART2_ROOT>; 1118 clock-names = "ipg", "per"; 1119 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1120 dma-names = "rx", "tx"; 1121 status = "disabled"; 1122 }; 1123 1124 flexcan1: can@308c0000 { 1125 compatible = "fsl,imx8mp-flexcan"; 1126 reg = <0x308c0000 0x10000>; 1127 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1129 <&clk IMX8MP_CLK_CAN1_ROOT>; 1130 clock-names = "ipg", "per"; 1131 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1132 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1133 assigned-clock-rates = <40000000>; 1134 fsl,clk-source = /bits/ 8 <0>; 1135 fsl,stop-mode = <&gpr 0x10 4>; 1136 status = "disabled"; 1137 }; 1138 1139 flexcan2: can@308d0000 { 1140 compatible = "fsl,imx8mp-flexcan"; 1141 reg = <0x308d0000 0x10000>; 1142 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1144 <&clk IMX8MP_CLK_CAN2_ROOT>; 1145 clock-names = "ipg", "per"; 1146 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1147 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1148 assigned-clock-rates = <40000000>; 1149 fsl,clk-source = /bits/ 8 <0>; 1150 fsl,stop-mode = <&gpr 0x10 5>; 1151 status = "disabled"; 1152 }; 1153 }; 1154 1155 crypto: crypto@30900000 { 1156 compatible = "fsl,sec-v4.0"; 1157 #address-cells = <1>; 1158 #size-cells = <1>; 1159 reg = <0x30900000 0x40000>; 1160 ranges = <0 0x30900000 0x40000>; 1161 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&clk IMX8MP_CLK_AHB>, 1163 <&clk IMX8MP_CLK_IPG_ROOT>; 1164 clock-names = "aclk", "ipg"; 1165 1166 sec_jr0: jr@1000 { 1167 compatible = "fsl,sec-v4.0-job-ring"; 1168 reg = <0x1000 0x1000>; 1169 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1170 status = "disabled"; 1171 }; 1172 1173 sec_jr1: jr@2000 { 1174 compatible = "fsl,sec-v4.0-job-ring"; 1175 reg = <0x2000 0x1000>; 1176 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1177 }; 1178 1179 sec_jr2: jr@3000 { 1180 compatible = "fsl,sec-v4.0-job-ring"; 1181 reg = <0x3000 0x1000>; 1182 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1183 }; 1184 }; 1185 1186 i2c1: i2c@30a20000 { 1187 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 reg = <0x30a20000 0x10000>; 1191 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1193 status = "disabled"; 1194 }; 1195 1196 i2c2: i2c@30a30000 { 1197 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 reg = <0x30a30000 0x10000>; 1201 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1202 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c3: i2c@30a40000 { 1207 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 reg = <0x30a40000 0x10000>; 1211 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1213 status = "disabled"; 1214 }; 1215 1216 i2c4: i2c@30a50000 { 1217 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 reg = <0x30a50000 0x10000>; 1221 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1223 status = "disabled"; 1224 }; 1225 1226 uart4: serial@30a60000 { 1227 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1228 reg = <0x30a60000 0x10000>; 1229 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1231 <&clk IMX8MP_CLK_UART4_ROOT>; 1232 clock-names = "ipg", "per"; 1233 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1234 dma-names = "rx", "tx"; 1235 status = "disabled"; 1236 }; 1237 1238 mu: mailbox@30aa0000 { 1239 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1240 reg = <0x30aa0000 0x10000>; 1241 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1243 #mbox-cells = <2>; 1244 }; 1245 1246 mu2: mailbox@30e60000 { 1247 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1248 reg = <0x30e60000 0x10000>; 1249 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1250 #mbox-cells = <2>; 1251 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; 1252 status = "disabled"; 1253 }; 1254 1255 i2c5: i2c@30ad0000 { 1256 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 reg = <0x30ad0000 0x10000>; 1260 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1262 status = "disabled"; 1263 }; 1264 1265 i2c6: i2c@30ae0000 { 1266 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 reg = <0x30ae0000 0x10000>; 1270 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1272 status = "disabled"; 1273 }; 1274 1275 usdhc1: mmc@30b40000 { 1276 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1277 reg = <0x30b40000 0x10000>; 1278 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1280 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1281 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1282 clock-names = "ipg", "ahb", "per"; 1283 fsl,tuning-start-tap = <20>; 1284 fsl,tuning-step = <2>; 1285 bus-width = <4>; 1286 status = "disabled"; 1287 }; 1288 1289 usdhc2: mmc@30b50000 { 1290 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1291 reg = <0x30b50000 0x10000>; 1292 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1294 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1295 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1296 clock-names = "ipg", "ahb", "per"; 1297 fsl,tuning-start-tap = <20>; 1298 fsl,tuning-step = <2>; 1299 bus-width = <4>; 1300 status = "disabled"; 1301 }; 1302 1303 usdhc3: mmc@30b60000 { 1304 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1305 reg = <0x30b60000 0x10000>; 1306 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1308 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1309 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1310 clock-names = "ipg", "ahb", "per"; 1311 fsl,tuning-start-tap = <20>; 1312 fsl,tuning-step = <2>; 1313 bus-width = <4>; 1314 status = "disabled"; 1315 }; 1316 1317 flexspi: spi@30bb0000 { 1318 compatible = "nxp,imx8mp-fspi"; 1319 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1320 reg-names = "fspi_base", "fspi_mmap"; 1321 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1323 <&clk IMX8MP_CLK_QSPI_ROOT>; 1324 clock-names = "fspi_en", "fspi"; 1325 assigned-clock-rates = <80000000>; 1326 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 sdma1: dma-controller@30bd0000 { 1333 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1334 reg = <0x30bd0000 0x10000>; 1335 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1337 <&clk IMX8MP_CLK_AHB>; 1338 clock-names = "ipg", "ahb"; 1339 #dma-cells = <3>; 1340 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1341 }; 1342 1343 fec: ethernet@30be0000 { 1344 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1345 reg = <0x30be0000 0x10000>; 1346 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1351 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1352 <&clk IMX8MP_CLK_ENET_TIMER>, 1353 <&clk IMX8MP_CLK_ENET_REF>, 1354 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1355 clock-names = "ipg", "ahb", "ptp", 1356 "enet_clk_ref", "enet_out"; 1357 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1358 <&clk IMX8MP_CLK_ENET_TIMER>, 1359 <&clk IMX8MP_CLK_ENET_REF>, 1360 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1361 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1362 <&clk IMX8MP_SYS_PLL2_100M>, 1363 <&clk IMX8MP_SYS_PLL2_125M>, 1364 <&clk IMX8MP_SYS_PLL2_50M>; 1365 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1366 fsl,num-tx-queues = <3>; 1367 fsl,num-rx-queues = <3>; 1368 nvmem-cells = <ð_mac1>; 1369 nvmem-cell-names = "mac-address"; 1370 fsl,stop-mode = <&gpr 0x10 3>; 1371 status = "disabled"; 1372 }; 1373 1374 eqos: ethernet@30bf0000 { 1375 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1376 reg = <0x30bf0000 0x10000>; 1377 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1379 interrupt-names = "macirq", "eth_wake_irq"; 1380 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1381 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1382 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1383 <&clk IMX8MP_CLK_ENET_QOS>; 1384 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1385 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1386 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1387 <&clk IMX8MP_CLK_ENET_QOS>; 1388 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1389 <&clk IMX8MP_SYS_PLL2_100M>, 1390 <&clk IMX8MP_SYS_PLL2_125M>; 1391 assigned-clock-rates = <0>, <100000000>, <125000000>; 1392 nvmem-cells = <ð_mac2>; 1393 nvmem-cell-names = "mac-address"; 1394 intf_mode = <&gpr 0x4>; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 aips5: bus@30c00000 { 1400 compatible = "fsl,aips-bus", "simple-bus"; 1401 reg = <0x30c00000 0x400000>; 1402 #address-cells = <1>; 1403 #size-cells = <1>; 1404 ranges; 1405 1406 spba-bus@30c00000 { 1407 compatible = "fsl,spba-bus", "simple-bus"; 1408 reg = <0x30c00000 0x100000>; 1409 #address-cells = <1>; 1410 #size-cells = <1>; 1411 ranges; 1412 1413 sai1: sai@30c10000 { 1414 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1415 reg = <0x30c10000 0x10000>; 1416 #sound-dai-cells = <0>; 1417 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1418 <&clk IMX8MP_CLK_DUMMY>, 1419 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1423 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1424 dma-names = "rx", "tx"; 1425 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1426 status = "disabled"; 1427 }; 1428 1429 sai2: sai@30c20000 { 1430 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1431 reg = <0x30c20000 0x10000>; 1432 #sound-dai-cells = <0>; 1433 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1434 <&clk IMX8MP_CLK_DUMMY>, 1435 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1438 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1439 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1440 dma-names = "rx", "tx"; 1441 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1442 status = "disabled"; 1443 }; 1444 1445 sai3: sai@30c30000 { 1446 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1447 reg = <0x30c30000 0x10000>; 1448 #sound-dai-cells = <0>; 1449 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1450 <&clk IMX8MP_CLK_DUMMY>, 1451 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1454 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1455 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1456 dma-names = "rx", "tx"; 1457 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1458 status = "disabled"; 1459 }; 1460 1461 sai5: sai@30c50000 { 1462 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1463 reg = <0x30c50000 0x10000>; 1464 #sound-dai-cells = <0>; 1465 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1466 <&clk IMX8MP_CLK_DUMMY>, 1467 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1469 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1470 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1471 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1472 dma-names = "rx", "tx"; 1473 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1474 status = "disabled"; 1475 }; 1476 1477 sai6: sai@30c60000 { 1478 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1479 reg = <0x30c60000 0x10000>; 1480 #sound-dai-cells = <0>; 1481 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1482 <&clk IMX8MP_CLK_DUMMY>, 1483 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1484 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1485 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1486 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1487 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1488 dma-names = "rx", "tx"; 1489 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1490 status = "disabled"; 1491 }; 1492 1493 sai7: sai@30c80000 { 1494 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1495 reg = <0x30c80000 0x10000>; 1496 #sound-dai-cells = <0>; 1497 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1498 <&clk IMX8MP_CLK_DUMMY>, 1499 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1500 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1501 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1502 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1503 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1504 dma-names = "rx", "tx"; 1505 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1506 status = "disabled"; 1507 }; 1508 1509 easrc: easrc@30c90000 { 1510 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1511 reg = <0x30c90000 0x10000>; 1512 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1513 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1514 clock-names = "mem"; 1515 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1516 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1517 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1518 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1519 dma-names = "ctx0_rx", "ctx0_tx", 1520 "ctx1_rx", "ctx1_tx", 1521 "ctx2_rx", "ctx2_tx", 1522 "ctx3_rx", "ctx3_tx"; 1523 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1524 fsl,asrc-rate = <8000>; 1525 fsl,asrc-format = <2>; 1526 status = "disabled"; 1527 }; 1528 1529 micfil: audio-controller@30ca0000 { 1530 compatible = "fsl,imx8mp-micfil"; 1531 reg = <0x30ca0000 0x10000>; 1532 #sound-dai-cells = <0>; 1533 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1537 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1538 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1539 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1540 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1541 <&clk IMX8MP_CLK_EXT3>; 1542 clock-names = "ipg_clk", "ipg_clk_app", 1543 "pll8k", "pll11k", "clkext3"; 1544 dmas = <&sdma2 24 25 0x80000000>; 1545 dma-names = "rx"; 1546 status = "disabled"; 1547 }; 1548 1549 aud2htx: aud2htx@30cb0000 { 1550 compatible = "fsl,imx8mp-aud2htx"; 1551 reg = <0x30cb0000 0x10000>; 1552 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1553 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1554 clock-names = "bus"; 1555 dmas = <&sdma2 26 2 0>; 1556 dma-names = "tx"; 1557 status = "disabled"; 1558 }; 1559 1560 xcvr: xcvr@30cc0000 { 1561 compatible = "fsl,imx8mp-xcvr"; 1562 reg = <0x30cc0000 0x800>, 1563 <0x30cc0800 0x400>, 1564 <0x30cc0c00 0x080>, 1565 <0x30cc0e00 0x080>; 1566 reg-names = "ram", "regs", "rxfifo", 1567 "txfifo"; 1568 interrupts = /* XCVR IRQ 0 */ 1569 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1570 /* XCVR IRQ 1 */ 1571 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1572 /* XCVR PHY - SPDIF wakeup IRQ */ 1573 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1574 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1575 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1576 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1577 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1578 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1579 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1580 dma-names = "rx", "tx"; 1581 resets = <&audio_blk_ctrl 0>; 1582 status = "disabled"; 1583 }; 1584 }; 1585 1586 sdma3: dma-controller@30e00000 { 1587 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1588 reg = <0x30e00000 0x10000>; 1589 #dma-cells = <3>; 1590 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1591 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1592 clock-names = "ipg", "ahb"; 1593 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1594 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1595 }; 1596 1597 sdma2: dma-controller@30e10000 { 1598 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1599 reg = <0x30e10000 0x10000>; 1600 #dma-cells = <3>; 1601 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1602 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1603 clock-names = "ipg", "ahb"; 1604 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1605 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1606 }; 1607 1608 audio_blk_ctrl: clock-controller@30e20000 { 1609 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1610 reg = <0x30e20000 0x10000>; 1611 #clock-cells = <1>; 1612 #reset-cells = <1>; 1613 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1614 <&clk IMX8MP_CLK_SAI1>, 1615 <&clk IMX8MP_CLK_SAI2>, 1616 <&clk IMX8MP_CLK_SAI3>, 1617 <&clk IMX8MP_CLK_SAI5>, 1618 <&clk IMX8MP_CLK_SAI6>, 1619 <&clk IMX8MP_CLK_SAI7>, 1620 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; 1621 clock-names = "ahb", 1622 "sai1", "sai2", "sai3", 1623 "sai5", "sai6", "sai7", "axi"; 1624 power-domains = <&pgc_audio>; 1625 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1626 <&clk IMX8MP_AUDIO_PLL2>; 1627 assigned-clock-rates = <393216000>, <361267200>; 1628 }; 1629 }; 1630 1631 noc: interconnect@32700000 { 1632 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1633 reg = <0x32700000 0x100000>; 1634 clocks = <&clk IMX8MP_CLK_NOC>; 1635 #interconnect-cells = <1>; 1636 operating-points-v2 = <&noc_opp_table>; 1637 1638 noc_opp_table: opp-table { 1639 compatible = "operating-points-v2"; 1640 1641 opp-200000000 { 1642 opp-hz = /bits/ 64 <200000000>; 1643 }; 1644 1645 /* Nominal drive mode maximum */ 1646 opp-800000000 { 1647 opp-hz = /bits/ 64 <800000000>; 1648 }; 1649 1650 /* Overdrive mode maximum */ 1651 opp-1000000000 { 1652 opp-hz = /bits/ 64 <1000000000>; 1653 }; 1654 }; 1655 }; 1656 1657 aips4: bus@32c00000 { 1658 compatible = "fsl,aips-bus", "simple-bus"; 1659 reg = <0x32c00000 0x400000>; 1660 #address-cells = <1>; 1661 #size-cells = <1>; 1662 ranges; 1663 1664 isi_0: isi@32e00000 { 1665 compatible = "fsl,imx8mp-isi"; 1666 reg = <0x32e00000 0x4000>; 1667 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1669 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1670 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1671 clock-names = "axi", "apb"; 1672 fsl,blk-ctrl = <&media_blk_ctrl>; 1673 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1674 status = "disabled"; 1675 1676 ports { 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 1680 port@0 { 1681 reg = <0>; 1682 1683 isi_in_0: endpoint { 1684 remote-endpoint = <&mipi_csi_0_out>; 1685 }; 1686 }; 1687 1688 port@1 { 1689 reg = <1>; 1690 1691 isi_in_1: endpoint { 1692 remote-endpoint = <&mipi_csi_1_out>; 1693 }; 1694 }; 1695 }; 1696 }; 1697 1698 isp_0: isp@32e10000 { 1699 compatible = "fsl,imx8mp-isp"; 1700 reg = <0x32e10000 0x10000>; 1701 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1703 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1704 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1705 clock-names = "isp", "aclk", "hclk"; 1706 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1707 fsl,blk-ctrl = <&media_blk_ctrl 0>; 1708 status = "disabled"; 1709 1710 ports { 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 port@1 { 1715 reg = <1>; 1716 }; 1717 }; 1718 }; 1719 1720 isp_1: isp@32e20000 { 1721 compatible = "fsl,imx8mp-isp"; 1722 reg = <0x32e20000 0x10000>; 1723 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1724 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1725 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1726 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1727 clock-names = "isp", "aclk", "hclk"; 1728 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1729 fsl,blk-ctrl = <&media_blk_ctrl 1>; 1730 status = "disabled"; 1731 1732 ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@1 { 1737 reg = <1>; 1738 }; 1739 }; 1740 }; 1741 1742 dewarp: dwe@32e30000 { 1743 compatible = "nxp,imx8mp-dw100"; 1744 reg = <0x32e30000 0x10000>; 1745 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1747 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1748 clock-names = "axi", "ahb"; 1749 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1750 }; 1751 1752 mipi_csi_0: csi@32e40000 { 1753 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1754 reg = <0x32e40000 0x10000>; 1755 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1756 clock-frequency = <250000000>; 1757 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1758 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1759 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1760 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1761 clock-names = "pclk", "wrap", "phy", "axi"; 1762 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1763 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1764 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1765 <&clk IMX8MP_CLK_24M>; 1766 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1767 status = "disabled"; 1768 1769 ports { 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 1773 port@0 { 1774 reg = <0>; 1775 }; 1776 1777 port@1 { 1778 reg = <1>; 1779 1780 mipi_csi_0_out: endpoint { 1781 remote-endpoint = <&isi_in_0>; 1782 }; 1783 }; 1784 }; 1785 }; 1786 1787 mipi_csi_1: csi@32e50000 { 1788 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1789 reg = <0x32e50000 0x10000>; 1790 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1791 clock-frequency = <250000000>; 1792 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1793 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1794 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1795 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1796 clock-names = "pclk", "wrap", "phy", "axi"; 1797 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1798 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1799 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1800 <&clk IMX8MP_CLK_24M>; 1801 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1802 status = "disabled"; 1803 1804 ports { 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 1808 port@0 { 1809 reg = <0>; 1810 }; 1811 1812 port@1 { 1813 reg = <1>; 1814 1815 mipi_csi_1_out: endpoint { 1816 remote-endpoint = <&isi_in_1>; 1817 }; 1818 }; 1819 }; 1820 }; 1821 1822 mipi_dsi: dsi@32e60000 { 1823 compatible = "fsl,imx8mp-mipi-dsim"; 1824 reg = <0x32e60000 0x400>; 1825 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1826 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1827 clock-names = "bus_clk", "sclk_mipi"; 1828 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1829 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1830 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1831 <&clk IMX8MP_CLK_24M>; 1832 assigned-clock-rates = <200000000>, <24000000>; 1833 samsung,pll-clock-frequency = <24000000>; 1834 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1835 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1836 status = "disabled"; 1837 1838 ports { 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 1842 port@0 { 1843 reg = <0>; 1844 1845 dsim_from_lcdif1: endpoint { 1846 remote-endpoint = <&lcdif1_to_dsim>; 1847 }; 1848 }; 1849 1850 port@1 { 1851 reg = <1>; 1852 1853 mipi_dsi_out: endpoint { 1854 }; 1855 }; 1856 }; 1857 }; 1858 1859 lcdif1: display-controller@32e80000 { 1860 compatible = "fsl,imx8mp-lcdif"; 1861 reg = <0x32e80000 0x10000>; 1862 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1863 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1864 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1865 clock-names = "pix", "axi", "disp_axi"; 1866 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1867 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1868 status = "disabled"; 1869 1870 port { 1871 lcdif1_to_dsim: endpoint { 1872 remote-endpoint = <&dsim_from_lcdif1>; 1873 }; 1874 }; 1875 }; 1876 1877 lcdif2: display-controller@32e90000 { 1878 compatible = "fsl,imx8mp-lcdif"; 1879 reg = <0x32e90000 0x10000>; 1880 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1882 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1883 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1884 clock-names = "pix", "axi", "disp_axi"; 1885 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1886 status = "disabled"; 1887 1888 port { 1889 lcdif2_to_ldb: endpoint { 1890 remote-endpoint = <&ldb_from_lcdif2>; 1891 }; 1892 }; 1893 }; 1894 1895 media_blk_ctrl: blk-ctrl@32ec0000 { 1896 compatible = "fsl,imx8mp-media-blk-ctrl", 1897 "syscon"; 1898 reg = <0x32ec0000 0x10000>; 1899 #address-cells = <1>; 1900 #size-cells = <1>; 1901 power-domains = <&pgc_mediamix>, 1902 <&pgc_mipi_phy1>, 1903 <&pgc_mipi_phy1>, 1904 <&pgc_mediamix>, 1905 <&pgc_mediamix>, 1906 <&pgc_mipi_phy2>, 1907 <&pgc_mediamix>, 1908 <&pgc_ispdwp>, 1909 <&pgc_ispdwp>, 1910 <&pgc_mipi_phy2>; 1911 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1912 "lcdif1", "isi", "mipi-csi2", 1913 "lcdif2", "isp", "dwe", 1914 "mipi-dsi2"; 1915 interconnects = 1916 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1917 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1918 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1919 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1920 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1921 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1922 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1923 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1924 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1925 "isi1", "isi2", "isp0", "isp1", 1926 "dwe"; 1927 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1928 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1929 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1930 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1931 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1932 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1933 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1934 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1935 clock-names = "apb", "axi", "cam1", "cam2", 1936 "disp1", "disp2", "isp", "phy"; 1937 1938 /* 1939 * The ISP maximum frequency is 400MHz in normal mode 1940 * and 500MHz in overdrive mode. The 400MHz operating 1941 * point hasn't been successfully tested yet, so set 1942 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. 1943 */ 1944 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1945 <&clk IMX8MP_CLK_MEDIA_APB>, 1946 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1947 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1948 <&clk IMX8MP_CLK_MEDIA_ISP>, 1949 <&clk IMX8MP_VIDEO_PLL1>; 1950 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1951 <&clk IMX8MP_SYS_PLL1_800M>, 1952 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1953 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1954 <&clk IMX8MP_SYS_PLL2_500M>; 1955 assigned-clock-rates = <500000000>, <200000000>, 1956 <0>, <0>, <500000000>, 1957 <1039500000>; 1958 #power-domain-cells = <1>; 1959 1960 lvds_bridge: bridge@5c { 1961 compatible = "fsl,imx8mp-ldb"; 1962 reg = <0x5c 0x4>, <0x128 0x4>; 1963 reg-names = "ldb", "lvds"; 1964 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1965 clock-names = "ldb"; 1966 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1967 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1968 status = "disabled"; 1969 1970 ports { 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 port@0 { 1975 reg = <0>; 1976 1977 ldb_from_lcdif2: endpoint { 1978 remote-endpoint = <&lcdif2_to_ldb>; 1979 }; 1980 }; 1981 1982 port@1 { 1983 reg = <1>; 1984 1985 ldb_lvds_ch0: endpoint { 1986 }; 1987 }; 1988 1989 port@2 { 1990 reg = <2>; 1991 1992 ldb_lvds_ch1: endpoint { 1993 }; 1994 }; 1995 }; 1996 }; 1997 }; 1998 1999 pcie_phy: pcie-phy@32f00000 { 2000 compatible = "fsl,imx8mp-pcie-phy"; 2001 reg = <0x32f00000 0x10000>; 2002 resets = <&src IMX8MP_RESET_PCIEPHY>, 2003 <&src IMX8MP_RESET_PCIEPHY_PERST>; 2004 reset-names = "pciephy", "perst"; 2005 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 2006 #phy-cells = <0>; 2007 status = "disabled"; 2008 }; 2009 2010 hsio_blk_ctrl: blk-ctrl@32f10000 { 2011 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 2012 reg = <0x32f10000 0x24>; 2013 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2014 <&clk IMX8MP_CLK_PCIE_ROOT>; 2015 clock-names = "usb", "pcie"; 2016 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 2017 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 2018 <&pgc_hsiomix>, <&pgc_pcie_phy>; 2019 power-domain-names = "bus", "usb", "usb-phy1", 2020 "usb-phy2", "pcie", "pcie-phy"; 2021 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 2022 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 2023 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 2024 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 2025 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 2026 #power-domain-cells = <1>; 2027 #clock-cells = <0>; 2028 }; 2029 2030 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 2031 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 2032 reg = <0x32fc0000 0x1000>; 2033 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2034 <&clk IMX8MP_CLK_HDMI_ROOT>, 2035 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2036 <&clk IMX8MP_CLK_HDMI_24M>, 2037 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 2038 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 2039 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 2040 <&pgc_hdmimix>, <&pgc_hdmimix>, 2041 <&pgc_hdmimix>, <&pgc_hdmimix>, 2042 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 2043 <&pgc_hdmimix>, <&pgc_hdmimix>; 2044 power-domain-names = "bus", "irqsteer", "lcdif", 2045 "pai", "pvi", "trng", 2046 "hdmi-tx", "hdmi-tx-phy", 2047 "hdcp", "hrv"; 2048 #power-domain-cells = <1>; 2049 }; 2050 2051 irqsteer_hdmi: interrupt-controller@32fc2000 { 2052 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 2053 reg = <0x32fc2000 0x1000>; 2054 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2055 interrupt-controller; 2056 #interrupt-cells = <1>; 2057 fsl,channel = <1>; 2058 fsl,num-irqs = <64>; 2059 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 2060 clock-names = "ipg"; 2061 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 2062 }; 2063 2064 hdmi_pvi: display-bridge@32fc4000 { 2065 compatible = "fsl,imx8mp-hdmi-pvi"; 2066 reg = <0x32fc4000 0x1000>; 2067 interrupt-parent = <&irqsteer_hdmi>; 2068 interrupts = <12>; 2069 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 2070 status = "disabled"; 2071 2072 ports { 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 2076 port@0 { 2077 reg = <0>; 2078 pvi_from_lcdif3: endpoint { 2079 remote-endpoint = <&lcdif3_to_pvi>; 2080 }; 2081 }; 2082 2083 port@1 { 2084 reg = <1>; 2085 pvi_to_hdmi_tx: endpoint { 2086 remote-endpoint = <&hdmi_tx_from_pvi>; 2087 }; 2088 }; 2089 }; 2090 }; 2091 2092 lcdif3: display-controller@32fc6000 { 2093 compatible = "fsl,imx8mp-lcdif"; 2094 reg = <0x32fc6000 0x1000>; 2095 interrupt-parent = <&irqsteer_hdmi>; 2096 interrupts = <8>; 2097 clocks = <&hdmi_tx_phy>, 2098 <&clk IMX8MP_CLK_HDMI_APB>, 2099 <&clk IMX8MP_CLK_HDMI_ROOT>; 2100 clock-names = "pix", "axi", "disp_axi"; 2101 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 2102 status = "disabled"; 2103 2104 port { 2105 lcdif3_to_pvi: endpoint { 2106 remote-endpoint = <&pvi_from_lcdif3>; 2107 }; 2108 }; 2109 }; 2110 2111 hdmi_tx: hdmi@32fd8000 { 2112 compatible = "fsl,imx8mp-hdmi-tx"; 2113 reg = <0x32fd8000 0x7eff>; 2114 interrupt-parent = <&irqsteer_hdmi>; 2115 interrupts = <0>; 2116 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2117 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2118 <&clk IMX8MP_CLK_32K>, 2119 <&hdmi_tx_phy>; 2120 clock-names = "iahb", "isfr", "cec", "pix"; 2121 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2122 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2123 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2124 reg-io-width = <1>; 2125 status = "disabled"; 2126 2127 ports { 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 port@0 { 2132 reg = <0>; 2133 2134 hdmi_tx_from_pvi: endpoint { 2135 remote-endpoint = <&pvi_to_hdmi_tx>; 2136 }; 2137 }; 2138 2139 port@1 { 2140 reg = <1>; 2141 /* Point endpoint to the HDMI connector */ 2142 }; 2143 }; 2144 }; 2145 2146 hdmi_tx_phy: phy@32fdff00 { 2147 compatible = "fsl,imx8mp-hdmi-phy"; 2148 reg = <0x32fdff00 0x100>; 2149 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2150 <&clk IMX8MP_CLK_HDMI_24M>; 2151 clock-names = "apb", "ref"; 2152 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2153 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2154 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2155 #clock-cells = <0>; 2156 #phy-cells = <0>; 2157 status = "disabled"; 2158 }; 2159 }; 2160 2161 pcie0: pcie: pcie@33800000 { 2162 compatible = "fsl,imx8mp-pcie"; 2163 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2164 reg-names = "dbi", "config"; 2165 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2166 <&clk IMX8MP_CLK_HSIO_AXI>, 2167 <&clk IMX8MP_CLK_PCIE_ROOT>; 2168 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2169 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2170 assigned-clock-rates = <10000000>; 2171 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2172 #address-cells = <3>; 2173 #size-cells = <2>; 2174 device_type = "pci"; 2175 bus-range = <0x00 0xff>; 2176 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2177 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2178 num-lanes = <1>; 2179 num-viewport = <4>; 2180 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2181 interrupt-names = "msi"; 2182 #interrupt-cells = <1>; 2183 interrupt-map-mask = <0 0 0 0x7>; 2184 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2185 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2186 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2187 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2188 fsl,max-link-speed = <3>; 2189 linux,pci-domain = <0>; 2190 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2191 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2192 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2193 reset-names = "apps", "turnoff"; 2194 phys = <&pcie_phy>; 2195 phy-names = "pcie-phy"; 2196 status = "disabled"; 2197 }; 2198 2199 pcie0_ep: pcie_ep: pcie-ep@33800000 { 2200 compatible = "fsl,imx8mp-pcie-ep"; 2201 reg = <0x33800000 0x100000>, 2202 <0x18000000 0x8000000>, 2203 <0x33900000 0x100000>, 2204 <0x33b00000 0x100000>; 2205 reg-names = "dbi", "addr_space", "dbi2", "atu"; 2206 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2207 <&clk IMX8MP_CLK_HSIO_AXI>, 2208 <&clk IMX8MP_CLK_PCIE_ROOT>; 2209 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2210 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2211 assigned-clock-rates = <10000000>; 2212 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2213 num-lanes = <1>; 2214 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2215 interrupt-names = "dma"; 2216 fsl,max-link-speed = <3>; 2217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2218 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2219 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2220 reset-names = "apps", "turnoff"; 2221 phys = <&pcie_phy>; 2222 phy-names = "pcie-phy"; 2223 num-ib-windows = <4>; 2224 num-ob-windows = <4>; 2225 status = "disabled"; 2226 }; 2227 2228 gpu3d: gpu@38000000 { 2229 compatible = "vivante,gc"; 2230 reg = <0x38000000 0x8000>; 2231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2232 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2233 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2234 <&clk IMX8MP_CLK_GPU_ROOT>, 2235 <&clk IMX8MP_CLK_GPU_AHB>; 2236 clock-names = "core", "shader", "bus", "reg"; 2237 #cooling-cells = <2>; 2238 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2239 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2240 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 2241 <&clk IMX8MP_SYS_PLL2_1000M>; 2242 assigned-clock-rates = <1000000000>, <1000000000>; 2243 power-domains = <&pgc_gpu3d>; 2244 }; 2245 2246 gpu2d: gpu@38008000 { 2247 compatible = "vivante,gc"; 2248 reg = <0x38008000 0x8000>; 2249 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2250 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2251 <&clk IMX8MP_CLK_GPU_ROOT>, 2252 <&clk IMX8MP_CLK_GPU_AHB>; 2253 clock-names = "core", "bus", "reg"; 2254 #cooling-cells = <2>; 2255 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2256 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2257 assigned-clock-rates = <1000000000>; 2258 power-domains = <&pgc_gpu2d>; 2259 }; 2260 2261 vpu_g1: video-codec@38300000 { 2262 compatible = "nxp,imx8mm-vpu-g1"; 2263 reg = <0x38300000 0x10000>; 2264 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2266 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2267 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2268 assigned-clock-rates = <800000000>; 2269 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2270 }; 2271 2272 vpu_g2: video-codec@38310000 { 2273 compatible = "nxp,imx8mq-vpu-g2"; 2274 reg = <0x38310000 0x10000>; 2275 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2276 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2277 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_VPU_PLL_OUT>; 2278 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2279 assigned-clock-rates = <700000000>, <700000000>; 2280 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2281 }; 2282 2283 vpumix_blk_ctrl: blk-ctrl@38330000 { 2284 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2285 reg = <0x38330000 0x100>; 2286 #power-domain-cells = <1>; 2287 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2288 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2289 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2290 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2291 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2292 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2293 clock-names = "g1", "g2", "vc8000e"; 2294 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>; 2295 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2296 assigned-clock-rates = <800000000>; 2297 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2298 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2299 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2300 interconnect-names = "g1", "g2", "vc8000e"; 2301 }; 2302 2303 npu: npu@38500000 { 2304 compatible = "vivante,gc"; 2305 reg = <0x38500000 0x200000>; 2306 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2308 <&clk IMX8MP_CLK_NPU_ROOT>, 2309 <&clk IMX8MP_CLK_ML_AXI>, 2310 <&clk IMX8MP_CLK_ML_AHB>; 2311 clock-names = "core", "shader", "bus", "reg"; 2312 #cooling-cells = <2>; 2313 power-domains = <&pgc_mlmix>; 2314 }; 2315 2316 gic: interrupt-controller@38800000 { 2317 compatible = "arm,gic-v3"; 2318 reg = <0x38800000 0x10000>, 2319 <0x38880000 0xc0000>; 2320 #interrupt-cells = <3>; 2321 interrupt-controller; 2322 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2323 interrupt-parent = <&gic>; 2324 }; 2325 2326 edacmc: memory-controller@3d400000 { 2327 compatible = "snps,ddrc-3.80a"; 2328 reg = <0x3d400000 0x400000>; 2329 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2330 }; 2331 2332 ddr-pmu@3d800000 { 2333 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2334 reg = <0x3d800000 0x400000>; 2335 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2336 }; 2337 2338 usb3_phy0: usb-phy@381f0040 { 2339 compatible = "fsl,imx8mp-usb-phy"; 2340 reg = <0x381f0040 0x40>; 2341 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2342 clock-names = "phy"; 2343 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2344 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2345 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2346 #phy-cells = <0>; 2347 status = "disabled"; 2348 }; 2349 2350 usb3_0: usb@32f10100 { 2351 compatible = "fsl,imx8mp-dwc3"; 2352 reg = <0x32f10100 0x8>, 2353 <0x381f0000 0x20>; 2354 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2355 <&clk IMX8MP_CLK_USB_SUSP>; 2356 clock-names = "hsio", "suspend"; 2357 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2358 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2359 #address-cells = <1>; 2360 #size-cells = <1>; 2361 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2362 ranges; 2363 status = "disabled"; 2364 2365 usb_dwc3_0: usb@38100000 { 2366 compatible = "snps,dwc3"; 2367 reg = <0x38100000 0x10000>; 2368 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2369 <&clk IMX8MP_CLK_USB_CORE_REF>, 2370 <&clk IMX8MP_CLK_USB_SUSP>; 2371 clock-names = "bus_early", "ref", "suspend"; 2372 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2373 phys = <&usb3_phy0>, <&usb3_phy0>; 2374 phy-names = "usb2-phy", "usb3-phy"; 2375 snps,gfladj-refclk-lpm-sel-quirk; 2376 snps,parkmode-disable-ss-quirk; 2377 }; 2378 2379 }; 2380 2381 usb3_phy1: usb-phy@382f0040 { 2382 compatible = "fsl,imx8mp-usb-phy"; 2383 reg = <0x382f0040 0x40>; 2384 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2385 clock-names = "phy"; 2386 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2387 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2388 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2389 #phy-cells = <0>; 2390 status = "disabled"; 2391 }; 2392 2393 usb3_1: usb@32f10108 { 2394 compatible = "fsl,imx8mp-dwc3"; 2395 reg = <0x32f10108 0x8>, 2396 <0x382f0000 0x20>; 2397 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2398 <&clk IMX8MP_CLK_USB_SUSP>; 2399 clock-names = "hsio", "suspend"; 2400 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2401 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2402 #address-cells = <1>; 2403 #size-cells = <1>; 2404 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2405 ranges; 2406 status = "disabled"; 2407 2408 usb_dwc3_1: usb@38200000 { 2409 compatible = "snps,dwc3"; 2410 reg = <0x38200000 0x10000>; 2411 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2412 <&clk IMX8MP_CLK_USB_CORE_REF>, 2413 <&clk IMX8MP_CLK_USB_SUSP>; 2414 clock-names = "bus_early", "ref", "suspend"; 2415 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2416 phys = <&usb3_phy1>, <&usb3_phy1>; 2417 phy-names = "usb2-phy", "usb3-phy"; 2418 snps,gfladj-refclk-lpm-sel-quirk; 2419 snps,parkmode-disable-ss-quirk; 2420 }; 2421 }; 2422 2423 dsp: dsp@3b6e8000 { 2424 compatible = "fsl,imx8mp-hifi4"; 2425 reg = <0x3b6e8000 0x88000>; 2426 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2427 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, 2428 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2429 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; 2430 clock-names = "ipg", "ocram", "core", "debug"; 2431 power-domains = <&pgc_audio>; 2432 mbox-names = "tx", "rx", "rxdb"; 2433 mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>; 2434 firmware-name = "imx/dsp/hifi4.bin"; 2435 resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; 2436 reset-names = "runstall"; 2437 status = "disabled"; 2438 }; 2439 }; 2440}; 2441