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/qemu/tcg/
H A Dtci.c100 static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) in tci_args_rr() argument
103 *r1 = extract32(insn, 12, 4); in tci_args_rr()
113 TCGReg *r1, MemOpIdx *m2) in tci_args_rrm() argument
116 *r1 = extract32(insn, 12, 4); in tci_args_rrm()
120 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) in tci_args_rrr() argument
123 *r1 = extract32(insn, 12, 4); in tci_args_rrr()
127 static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) in tci_args_rrs() argument
130 *r1 = extract32(insn, 12, 4); in tci_args_rrs()
134 static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, in tci_args_rrbb() argument
138 *r1 = extract32(insn, 12, 4); in tci_args_rrbb()
[all …]
/qemu/target/tricore/
H A Dtranslate.c212 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_ld() argument
217 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); in gen_offset_ld()
220 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_st() argument
225 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); in gen_offset_st()
261 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_st_preincr() argument
266 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); in gen_st_preincr()
270 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_ld_preincr() argument
275 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); in gen_ld_preincr()
368 tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
376 static inline void gen_mtcr(DisasContext *ctx, TCGv r1, in gen_mtcr() argument
[all …]
H A Dop_helper.c263 target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1, in helper_add_ssov() argument
266 int64_t t1 = sextract64(r1, 0, 32); in helper_add_ssov()
272 uint64_t helper_add64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2) in helper_add64_ssov() argument
277 result = r1 + r2; in helper_add64_ssov()
278 ovf = (result ^ r1) & ~(r1 ^ r2); in helper_add64_ssov()
285 if ((int64_t)r1 >= 0) { in helper_add64_ssov()
297 target_ulong helper_add_h_ssov(CPUTriCoreState *env, target_ulong r1, in helper_add_h_ssov() argument
302 ret_hw0 = sextract32(r1, 0, 16) + sextract32(r2, 0, 16); in helper_add_h_ssov()
303 ret_hw1 = sextract32(r1, 16, 16) + sextract32(r2, 16, 16); in helper_add_h_ssov()
307 uint32_t helper_addr_h_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2_l, in helper_addr_h_ssov() argument
[all …]
/qemu/tests/tcg/s390x/
H A Ddiv.c7 register int32_t r1 asm("r1") = -4241; in test_dr()
11 : [r0] "+r" (r0), [r1] "+r" (r1) in test_dr()
14 q = r1; in test_dr()
23 register uint32_t r1 asm("r1") = 4243; in test_dlr()
27 : [r0] "+r" (r0), [r1] "+r" (r1) in test_dlr()
30 q = r1; in test_dlr()
39 register int64_t r1 asm("r1") = -4241; in test_dsgr()
43 : [r0] "+r" (r0), [r1] "+r" (r1) in test_dsgr()
46 q = r1; in test_dsgr()
55 register uint64_t r1 asm("r1") = 4243; in test_dlgr()
[all …]
H A Drxsbg.c10 rxsbg(unsigned long *r1, unsigned long r2, int i3, int i4, int i5, int *cc) in rxsbg() argument
12 asm("rxsbg %[r1],%[r2],%[i3],%[i4],%[i5]\n" in rxsbg()
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in rxsbg()
22 unsigned long r1 = 6; in test_cc0() local
25 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc0()
26 assert(r1 == 6); in test_cc0()
32 unsigned long r1 = 2; in test_cc1() local
35 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc1()
36 assert(r1 == 2); in test_cc1()
H A Dprecise-smc-softmmu.S19 lghi %r1,21
26 sgr %r1,%r1 /* this becomes `agr %r1,%r1` */
27 cgijne %r1,42,failure
36 sgr %r1,%r1 /* this becomes `d %r0,zero` */
49 agr %r1,%r1 /* replaces sgr */
H A Dper.S38 larl %r1, d1
46 larl %r1, d2
47 j2: br %r1
53 larl %r1, d3
54 clr %r1, %r2 /* d3 != 0 */
61 larl %r1, d4
62 clr %r1, %r2 /* d4 != 0 */
63 j4: bner %r1
78 clg %r1, program_old_psw+8 /* psw.addr updated to dest? */
H A Depsw.c11 unsigned long r1 = 0x1234567887654321UL, r2 = 0x8765432112345678UL; in main() local
13 asm("cr %[r1],%[r2]\n" /* cc = 1 */ in main()
14 "epsw %[r1],%[r2]" in main()
15 : [r1] "+r" (r1), [r2] "+r" (r2) : : "cc"); in main()
18 r1 &= ~0x40000008UL; in main()
19 assert(r1 == 0x1234567807051001UL); in main()
H A Dlcbb.c10 lcbb(long *r1, void *dxb2, int m3, int *cc) in lcbb() argument
12 asm("lcbb %[r1],%[dxb2],%[m3]\n" in lcbb()
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in lcbb()
25 long r1 = 0xfedcba9876543210; in test_lcbb() local
28 lcbb(&r1, p, m3, &cc); in test_lcbb()
29 assert(r1 == (0xfedcba9800000000 | exp_r1)); in test_lcbb()
H A Dexrl-trt.c8 register uint64_t r1 asm("r1") = 0xffffffffffffffffull; in main()
25 : [r1] "+r" (r1), in main()
37 if ((char *)r1 != &op1[5]) { in main()
38 write(1, "bad r1\n", 7); in main()
H A Dexrl-trtr.c8 register uint64_t r1 asm("r1") = 0xffffffffffffffffull; in main()
25 : [r1] "+r" (r1), in main()
37 if ((char *)r1 != &op1[1]) { in main()
38 write(1, "bad r1\n", 7); in main()
H A Dmc.S29 llgc %r1,ilc
30 sgr %r0,%r1
31 larl %r1,mc_monitor_event /* dispatch based on old PSW */
32 cgrje %r0,%r1,pgm_monitor_event
33 larl %r1,mc_specification
34 cgrje %r0,%r1,pgm_specification
H A Dlocfhr.c10 locfhr(long r1, long r2, int m3, int cc) in locfhr() argument
14 "locfhr %[r1],%[r2],%[m3]\n" in locfhr()
15 : [r1] "+r" (r1) in locfhr()
18 return r1; in locfhr()
H A Dcgebra.c13 long long r1; in main() local
17 asm("cgebra %[r1],%[m3],%[r2],%[m4]\n" in main()
19 : [r1] "=r" (r1) in main()
27 assert(r1 == 0x7fffffffffffffffLL); in main()
/qemu/pc-bios/s390-ccw/
H A Dstart.S31 lgr %r1,%r2
34 xc 0(256,%r1),0(%r1)
35 la %r1,256(%r1)
47 xc 0(1,%r1),0(%r1)
56 larl %r1,disabled_wait_psw
57 lpswe 0(%r1)
73 larl %r1,external_new_code
74 stg %r1,0x1b8
75 larl %r1,external_new_mask
76 mvc 0x1b0(8),0(%r1)
[all …]
/qemu/tests/tcg/arm/system/
H A Dboot.S10 * R1 - semihosting parameter
58 ldreq r1, =ADP_Stopped_ApplicationExit // if r0 == 0
59 ldrne r1, =ADP_Stopped_InternalError // else
95 * r1 - address
121 ldr r1, =.text
123 and r2, r1, r2
132 ldr r1, =.data
134 and r2, r1, r2
194 STMFD sp!, {r0-r1} // push r0, r1 onto stack
195 mov r1, sp
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc26 C(0x1a00, AR, RR_a, Z, r1, r2, new, r1_32, add, adds32)
28 C(0x5a00, A, RX_a, Z, r1, m2_32s, new, r1_32, add, adds32)
29 C(0xe35a, AY, RXY_a, LD, r1, m2_32s, new, r1_32, add, adds32)
30 C(0xb908, AGR, RRE, Z, r1, r2, r1, 0, add, adds64)
31 C(0xb918, AGFR, RRE, Z, r1, r2_32s, r1, 0, add, adds64)
32 C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
33 C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
34 C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
44 C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32)
47 C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
[all …]
H A Dmisc_helper.c105 uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2) in HELPER()
108 int r = sclp_service_call(env_archcpu(env), r1, r2); in HELPER()
116 void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num) in HELPER()
137 handle_diag_308(env, r1, r3, GETPC()); in HELPER()
143 r = handle_diag_288(env, r1, r3); in HELPER()
275 uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) in HELPER()
279 const uint32_t sel2 = r1 & STSI_R1_SEL2_MASK; in HELPER()
291 if ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK)) { in HELPER()
422 uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, in HELPER()
429 cc = handle_sigp(env, order_code & SIGP_ORDER_MASK, r1, r3); in HELPER()
[all …]
H A Dtranslate.c1036 #define IF_AFP1 0x0001 /* r1 is a fp reg for HFP/FPS instructions */
1501 int r1 = get_field(s, r1); in op_bct32() local
1511 tcg_gen_subi_i64(t, regs[r1], 1); in op_bct32()
1512 store_reg32_i64(r1, t); in op_bct32()
1523 int r1 = get_field(s, r1); in op_bcth() local
1532 tcg_gen_shri_i64(t, regs[r1], 32); in op_bcth()
1534 store_reg32h_i64(r1, t); in op_bcth()
1544 int r1 = get_field(s, r1); in op_bct64() local
1552 tcg_gen_subi_i64(regs[r1], regs[r1], 1); in op_bct64()
1553 c.u.s64.a = regs[r1]; in op_bct64()
[all …]
H A Dmem_helper.c687 uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask, in HELPER()
693 HELPER_LOG("%s: r1 0x%x mask 0x%x addr 0x%" PRIx64 "\n", __func__, r1, in HELPER()
704 uint8_t r = extract32(r1, 24, 8); in HELPER()
717 r1 <<= 8; in HELPER()
804 /* search string (c is byte to search, r2 is string, r1 end of string) */
805 void HELPER(srst)(CPUS390XState *env, uint32_t r1, uint32_t r2) in HELPER()
818 end = get_address(env, r1); in HELPER()
824 /* Character not found. R1 & R2 are unmodified. */ in HELPER()
830 /* Character found. Set R1 to the location; R2 is unmodified. */ in HELPER()
832 set_address(env, r1, str + len); in HELPER()
[all …]
/qemu/target/s390x/
H A Ddiag.c28 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3) in handle_diag_288() argument
30 uint64_t func = env->regs[r1]; in handle_diag_288()
31 uint64_t timeout = env->regs[r1 + 1]; in handle_diag_288()
37 if (r1 % 2 || action != 0) { in handle_diag_288()
56 static int diag308_parm_check(CPUS390XState *env, uint64_t r1, uint64_t addr, in diag308_parm_check() argument
63 if ((r1 & 1) || (addr & ~TARGET_PAGE_MASK)) { in diag308_parm_check()
76 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) in handle_diag_308() argument
81 uint64_t addr = env->regs[r1]; in handle_diag_308()
113 if (diag308_parm_check(env, r1, addr, ra, false)) { in handle_diag_308()
124 env->regs[r1 + 1] = DIAG_308_RC_INVALID; in handle_diag_308()
[all …]
/qemu/tests/tcg/hexagon/
H A Dtest_vmaxh.S7 * input: r1 = 0x00010003 r0 = 0x00010005 r3 = 0x00030002 r2 = 0x00020007
8 * output: r1 = 0x00030003 r0 = 0x00020007
17 r1 = #65539 define
24 r1:0 = vmaxh(r1:0, r3:2)
33 p0 = cmp.eq(r1, #196611); if (p0.new) jump:t pass
H A Dtest_vminh.S7 * input: r1 = 0x00010003 r0 = 0x00010005 r3 = 0x00030002 r2 = 0x00020007
8 * output: r1 = 0x00010002 r0 = 0x00010005
17 r1 = #65539 define
24 r1:0 = vminh(r1:0, r3:2)
33 p0 = cmp.eq(r1, #65538); if (p0.new) jump:t pass
H A Dtest_lsr.S9 r1 = #2147483647 define
15 r0 &= lsr(r1, r2)
25 r1 = #0x00000000 define
31 r1:0 = lsl(r1:0, r2)
/qemu/pc-bios/vof/
H A Dentry.S25 stwu %r1,-112(%r1)
26 stw %r31,104(%r1)
31 lwz %r31,104(%r1)
32 addi %r1,%r1,112

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