xref: /linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml (revision 4f9786035f9e519db41375818e1d0b5f20da2f10) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: GENI Serial Engine QUP Wrapper Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
14 is a programmable module for supporting a wide range of serial interfaces
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
17 Wrapper controller is modeled as a node with zero or more child nodes each
18 representing a serial engine.
19
20properties:
21  compatible:
22    enum:
23      - qcom,geni-se-qup
24      - qcom,geni-se-i2c-master-hub
25
26  reg:
27    description: QUP wrapper common register address and length.
28    maxItems: 1
29
30  clock-names:
31    minItems: 1
32    maxItems: 2
33
34  clocks:
35    minItems: 1
36    maxItems: 2
37
38  "#address-cells":
39    const: 2
40
41  "#size-cells":
42    const: 2
43
44  ranges: true
45
46  interconnects:
47    maxItems: 1
48
49  interconnect-names:
50    const: qup-core
51
52  iommus:
53    maxItems: 1
54
55  dma-coherent: true
56
57  firmware-name:
58    maxItems: 1
59    description: Specify the name of the QUP firmware to load.
60
61required:
62  - compatible
63  - reg
64  - clock-names
65  - clocks
66  - "#address-cells"
67  - "#size-cells"
68  - ranges
69
70patternProperties:
71  "spi@[0-9a-f]+$":
72    type: object
73    description: GENI serial engine based SPI controller. SPI in master mode
74                 supports up to 50MHz, up to four chip selects, programmable
75                 data path from 4 bits to 32 bits and numerous protocol
76                 variants.
77    $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
78
79  "i2c@[0-9a-f]+$":
80    type: object
81    description: GENI serial engine based I2C controller.
82    $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
83
84  "serial@[0-9a-f]+$":
85    type: object
86    description: GENI Serial Engine based UART Controller.
87    $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
88
89allOf:
90  - if:
91      properties:
92        compatible:
93          contains:
94            const: qcom,geni-se-i2c-master-hub
95    then:
96      properties:
97        clock-names:
98          items:
99            - const: s-ahb
100
101        clocks:
102          items:
103            - description: Slave AHB Clock
104
105        iommus: false
106
107      patternProperties:
108        "spi@[0-9a-f]+$": false
109        "serial@[0-9a-f]+$": false
110    else:
111      properties:
112        clock-names:
113          items:
114            - const: m-ahb
115            - const: s-ahb
116
117        clocks:
118          items:
119            - description: Master AHB Clock
120            - description: Slave AHB Clock
121
122additionalProperties: false
123
124examples:
125  - |
126    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
127    #include <dt-bindings/interrupt-controller/arm-gic.h>
128
129    soc {
130        #address-cells = <2>;
131        #size-cells = <2>;
132
133        geniqup@8c0000 {
134            compatible = "qcom,geni-se-qup";
135            reg = <0 0x008c0000 0 0x6000>;
136            clock-names = "m-ahb", "s-ahb";
137            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
138                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
139            #address-cells = <2>;
140            #size-cells = <2>;
141            ranges;
142            firmware-name = "qcom/sa8775p/qupv3fw.elf";
143
144            i2c0: i2c@a94000 {
145                compatible = "qcom,geni-i2c";
146                reg = <0 0xa94000 0 0x4000>;
147                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
148                clock-names = "se";
149                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
150                pinctrl-names = "default", "sleep";
151                pinctrl-0 = <&qup_1_i2c_5_active>;
152                pinctrl-1 = <&qup_1_i2c_5_sleep>;
153                #address-cells = <1>;
154                #size-cells = <0>;
155            };
156
157            uart0: serial@a88000 {
158                compatible = "qcom,geni-uart";
159                reg = <0 0xa88000 0 0x7000>;
160                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
161                clock-names = "se";
162                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
163                pinctrl-names = "default", "sleep";
164                pinctrl-0 = <&qup_1_uart_3_active>;
165                pinctrl-1 = <&qup_1_uart_3_sleep>;
166            };
167        };
168    };
169
170...
171