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/qemu/docs/system/openrisc/
H A Dcpu-features.rst10 - Programmable Interrupt Controller (PIC)
/qemu/include/hw/nvram/
H A Dbcm2835_otp.h2 * BCM2835 One-Time Programmable (OTP) Memory
H A Dnpcm7xx_otp.h22 /* Each OTP module holds 8192 bits of one-time programmable storage */
/qemu/docs/system/arm/
H A Dxlnx-zynq.rst5 processing system (PS) and AMD programmable logic (PL) in a single device.
H A Dxlnx-versal-virt.rst6 peripherals in a Processing System (PS) with runtime programmable
36 - eFUSE (3072 bytes of one-time field-programmable bit array)
/qemu/include/hw/arm/
H A Dmsf2-soc.h43 * System timer consists of two programmable 32-bit
/qemu/include/hw/misc/
H A Dsifive_u_otp.h2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
/qemu/include/hw/pci-host/
H A Dpam.h33 * PAM: Programmable Attribute Map registers
/qemu/linux-user/ppc/
H A Dcpu_loop.c281 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ in cpu_loop()
282 cpu_abort(cs, "Programmable interval timer interrupt " in cpu_loop()
/qemu/hw/nvram/
H A Dbcm2835_otp.c2 * BCM2835 One-Time Programmable (OTP) Memory
/qemu/target/riscv/
H A Dpmu.c31 * To keep it simple, any event can be mapped to any programmable counters in
33 * using programmable counters. In that case, mcycle & minstret must continue
H A Dcpu.h534 /* A bitmask of Available programmable counters */
/qemu/docs/system/ppc/
H A Dppce500.rst14 * Multicore Programmable Interrupt Controller (MPIC) with MSI support
/qemu/hw/misc/
H A Dsifive_u_otp.c2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
/qemu/hw/char/
H A Dcmsdk-apb-uart.c85 /* This UART is always 8N1 but the baud rate is programmable. */ in uart_update_parameters()
/qemu/linux-headers/asm-s390/
H A Dkvm.h582 __u64 todpr; /* tod programmable register [ARCH0] */
/qemu/hw/timer/
H A Dsse-counter.c21 * 88-bit precision (64.24 fixed point), with a programmable scale factor.
/qemu/docs/system/riscv/
H A Dsifive_u.rst22 * 1 One-Time Programmable (OTP) memory with stored serial number
/qemu/hw/arm/
H A Dmusca.c218 * For now we implement the flash regions as ROM (ie not programmable) in make_mpc()
/qemu/docs/system/devices/
H A Dcxl.rst216 programmable HDM decoders to route memory accesses either to
/qemu/docs/devel/
H A Dclocks.rst280 have guest-programmable frequency multipliers or dividers.
/qemu/target/ppc/
H A Dexcp_helper.c497 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ in powerpc_excp_40x()
2044 /* Programmable interval timer on embedded PowerPC */ in ppc_next_unmasked_interrupt()
2376 case PPC_INTERRUPT_PIT: /* Programmable interval timer on embedded ppc */ in ppc_deliver_interrupt()
/qemu/target/s390x/tcg/
H A Dmisc_helper.c242 /* Set Tod Programmable Field */
/qemu/hw/net/
H A Ddp8393x.c412 /* Handle programmable interrupt */ in dp8393x_do_transmit_packets()
/qemu/hw/intc/
H A Darm_gicv3_redist.c492 * implement LPIs) so Enable_LPIs is programmable. in gicr_writel()

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