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/qemu/docs/system/
H A Dcpu-models-mips.rst.inc17 MIPS32 Processor (Release 6, 2015)
20 MIPS32 Processor (P5600, 2014)
23 MIPS32 Processor (M14K, 2009)
26 MIPS32 Processor (74K, 2007)
29 MIPS32 Processor (34K, 2006)
32 MIPS32 Processor (24K, 2003)
35 MIPS32 Processor (4K, 1999)
49 MIPS64 Processor (Release 6, 2014)
52 MIPS64 Processor (Loongson 2, 2006)
55 MIPS64 Processor (Loongson 2, 2008)
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H A Dcpu-models-x86.rst.inc75 Intel Xeon Processor (ClearwaterForest, 2025)
78 Intel Xeon Processor (SierraForest, 2024), SierraForest-v2 mitigates
82 Intel Xeon Processor (GraniteRapids, 2024)
85 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
86 or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
90 Intel Xeon Processor (Skylake, 2016)
93 Intel Core Processor (Skylake, 2015)
96 Intel Core Processor (Broadwell, 2014)
99 Intel Core Processor (Haswell, 2013)
215 processor is vulnerable, use the Intel VERW instruction (a
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/qemu/tests/functional/acpi-bits/bits-tests/
H A Dtestacpi.py242 …testsuite.add_test("ACPI _MAT (Multiple APIC Table Entry) under Processor objects", test_mat, subm…
59 # Find the ProcId defined by the processor object
60 processor = acpi.evaluate(cpupath)
61 # Find the UID defined by the processor object's _UID method
71 …testsuite.test("{} Processor declaration ProcId = _MAT ProcId".format(cpupath), processor.ProcId =…
72 …t_detail("{} ProcId ({:#02x}) != _MAT ProcId ({:#02x})".format(cpupath, processor.ProcId, subtable…
73 testsuite.print_detail("Processor Declaration: {}".format(processor))
75 …st("{} with local APIC in _MAT has local APIC in MADT".format(cpupath), processor.ProcId in procid…
76 …ite.test("{} ApicId derived using Processor declaration ProcId = _MAT ApicId".format(cpupath), pro…
77 … MADT ({:#02x}) != _MAT ApicId ({:#02x})".format(cpupath, procid_apicid[processor.ProcId], subtabl…
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/qemu/docs/system/riscv/
H A Dmicroblaze-v-generic.rst3 The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
6 compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
7 replacement for the classic MicroBlaze™ processor in existing RTL designs).
H A Dshakti-c.rst7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
8 is a 64bit RV64GCSUN processor core.
/qemu/target/ppc/translate/
H A Dprocessor-ctrl-impl.c.inc21 * Processor Control Instructions
28 * Before Power ISA 2.07, processor control instructions were only
29 * implemented in the "Embedded.Processor Control" category.
52 * Before Power ISA 2.07, processor control instructions were only
53 * implemented in the "Embedded.Processor Control" category.
/qemu/hw/timer/
H A Dslavio_timer.c57 /* processor only */
111 if (t->limit == 0) { /* free-run system or processor counter */ in slavio_timer_get_out()
180 // only available in processor counter/timer in slavio_timer_mem_readl()
287 unsigned int processor = 1 << i; in slavio_timer_mem_writel() local
291 // check for a change in timer mode for this processor in slavio_timer_mem_writel()
292 if ((val & processor) != (s->cputimer_mode & processor)) { in slavio_timer_mem_writel()
293 if (val & processor) { // counter -> user timer in slavio_timer_mem_writel()
306 s->cputimer_mode |= processor; in slavio_timer_mem_writel()
313 s->cputimer_mode &= ~processor; in slavio_timer_mem_writel()
H A Dtrace-events9 slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer se…
11 slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
12 slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
13 slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to u…
14 slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user time…
/qemu/hw/i386/
H A Dacpi-common.c50 /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */ in pc_madt_cpu_entry()
53 build_append_int_noprefix(entry, uid, 1); /* ACPI Processor ID */ in pc_madt_cpu_entry()
57 /* Rev 4.0, 5.2.12.12 Processor Local x2APIC Structure */ in pc_madt_cpu_entry()
63 build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ in pc_madt_cpu_entry()
146 /* ACPI Processor UID */ in acpi_build_madt()
156 /* ACPI Processor ID */ in acpi_build_madt()
/qemu/include/hw/xtensa/
H A Dxtensa-isa.h42 * particular Xtensa processor. For example, the set of valid
53 * . stateOperands - information about processor state instruction operands
56 * . processor states - internal processor state information
58 * . interfaces - TIE interfaces that are external to the processor
251 * Get the number of stages in the processor's pipeline. The pipeline
255 * actual processor hardware, e.g., the hardware may have additional
262 /* Get the number of various entities that are defined for this processor. */
678 /* Processor States. */
685 /* Get the name for a processor state. Returns null on error. */
691 * Get the bit width for a processor state.
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/qemu/tests/functional/
H A Dtest_mem_addr_space.py3 # Check for crash when using memory beyond the available guest processor
46 With pse36 feature ON, a processor has 36 bits of addressing. So it can
54 that the processor can address all memory directly.
74 With pae feature ON, a processor has 36 bits of addressing. So it can
144 Pentium processor has 32 bits of addressing without pse36 or pae
194 processor address space, it has to be 1012 GiB , that is 12 GiB
266 AMD processor with 41 bits. Max cpu hw address = 2 TiB.
291 AMD processor with 41 bits. Max cpu hw address = 2 TiB.
314 alignment constraints with 40 bits (1 TiB) of processor physical bits.
/qemu/docs/specs/
H A Dfsi.rst13 FSI allows a service processor access to the internal buses of a host POWER
14 processor to perform configuration or debugging. FSI has long existed in POWER
18 Working backwards from the POWER processor, the fundamental pieces of interest
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
H A Dppc-xive.rst5 The POWER9 processor comes with a new interrupt controller
23 (SC). These are found in PCI PHBs, in the Processor Service
26 the chip/processor. They are configured to feed the IVRE with
118 the processor HW threads. It maintains the interrupt context state of
139 - Current Processor Priority (CPPR)
166 The PIPR is then compared to the Current Processor Priority
/qemu/linux-user/s390x/
H A Dtarget_mman.h2 * arch/s390/include/asm/processor.h:
15 * arch/s390/include/asm/processor.h:
H A Dtarget_proc.h22 * Keep the code structure close to arch/s390/kernel/processor.c.
73 dprintf(fd, "processor %d: " in show_cpu_summary()
/qemu/hw/acpi/
H A Dcpu_hotplug.c147 * cpu_id = Arg1 = Processor ID in build_legacy_cpu_hotplug_aml()
156 /* Update the processor id, lapic id, and enable/disable status */ in build_legacy_cpu_hotplug_aml()
194 Aml *idx = aml_local(0); /* Processor ID / APIC ID iterator */ in build_legacy_cpu_hotplug_aml()
277 /* build Processor object for each processor */ in build_legacy_cpu_hotplug_aml()
/qemu/linux-user/arm/
H A Dtarget_proc.h67 "processor\t: %d\n" in open_cpuinfo()
68 "model name\t: ARMv%d Processor rev %d (%s)\n" in open_cpuinfo()
/qemu/hw/misc/
H A Dimx6_src.c188 /* We clear the reset bits as the processor changed state */ in imx6_src_write()
201 /* We clear the reset bits as the processor changed state */ in imx6_src_write()
214 /* We clear the reset bits as the processor changed state */ in imx6_src_write()
/qemu/hw/pci-host/
H A Dxen_igd_pt.c43 {0x50, 2}, /* SNB: processor graphics control register */
44 {0x52, 2}, /* processor graphics control register */
/qemu/linux-user/m68k/
H A Dtarget_mman.h1 /* arch/m68k/include/asm/processor.h */
/qemu/scripts/kvm/
H A Dvmxcap138 name = 'primary processor-based controls',
168 name = 'secondary processor-based controls',
202 name = 'tertiary processor-based controls',
/qemu/linux-user/openrisc/
H A Dtarget_mman.h2 * arch/openrisc/include/asm/processor.h:
/qemu/linux-user/microblaze/
H A Dtarget_mman.h2 * arch/microblaze/include/asm/processor.h:
/qemu/linux-user/riscv/
H A Dtarget_mman.h2 * arch/loongarch/include/asm/processor.h:
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
81 #define XCHAL_HAVE_PRID 1 /* processor ID register */
126 Processor Generator */
334 * These macros describe how Xtensa processor interrupt numbers
338 * See the Xtensa processor databook for more details.

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