Searched full:processor (Results 76 – 100 of 262) sorted by relevance
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| /qemu/include/hw/ppc/ |
| H A D | pnv_psi.h | 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
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| H A D | openpic.h | 156 uint32_t pir; /* Processor initialization register */
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| /qemu/docs/devel/ |
| H A D | atomics.rst | 67 and the operations of each individual processor appear in this sequence
140 stores: both the compiler and the processor are free to reorder
203 the processor will guarantee that the first LOAD will appear to happen
216 needs a processor barrier. On strongly-ordered architectures such
480 because the read of ``y`` can be moved (by either the processor or the
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| H A D | lockcnt.rst | 102 processor and the compiler see all required memory barriers.
256 list during the walk. ``QLIST_FOREACH_RCU`` ensures that the processor and
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| /qemu/hw/char/ |
| H A D | diva-gsp.c | 7 * GSP stands for "Guardian Service Processor". Later products were marketed
8 * "Management Processor" (MP).
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| /qemu/target/i386/nvmm/ |
| H A D | nvmm-accel-ops.c | 75 * Abort the call to run the virtual processor by another thread, and to
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| /qemu/docs/system/ppc/ |
| H A D | powernv.rst | 18 * Multi processor support for POWER8, POWER8NVL and POWER9.
21 * Processor Service Interface (PSI) Controller.
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| /qemu/qapi/ |
| H A D | machine-common.json | 28 # logical processor level. The @threads option in
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| /qemu/hw/usb/ |
| H A D | hcd-uhci.h | 7 * Magor rewrite of the UHCI data structures parser and frame processor
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| H A D | chipidea.c | 153 * Offsets used were taken from i.MX7Dual Applications Processor in chipidea_class_init()
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| /qemu/include/hw/cpu/ |
| H A D | cluster.h | 36 * controller processor) they should be in different clusters.
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| /qemu/target/ppc/ |
| H A D | tcg-excp_helper.c | 257 * Machine check codes can be found in processor User Manual or in ppc_cpu_do_transaction_failed()
650 /* Embedded.Processor Control */
707 /* Server Processor Control */
826 * multi-threaded processor
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| /qemu/target/hexagon/ |
| H A D | README | 2 processor(DSP). We also support Hexagon Vector eXtensions (HVX). HVX
253 structure, and update the visible processor state when we commit the packet.
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| /qemu/hw/scsi/ |
| H A D | vmw_pvscsi.h | 275 * - vcpuHint: vcpuId of the processor that will be most likely waiting for the
279 * the processor that initiated the i/o as a likely candidate for the vcpu
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| /qemu/include/standard-headers/linux/ |
| H A D | virtio_ids.h | 38 #define VIRTIO_ID_RPMSG 7 /* virtio remote processor messaging */
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| /qemu/docs/system/arm/ |
| H A D | sabrelite.rst | 6 Applications Processor.
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| /qemu/target/sh4/ |
| H A D | cpu.h | 226 * @pvr: Processor Version Register
227 * @prr: Processor Revision Register
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| /qemu/util/ |
| H A D | stats64.c | 15 #include "qemu/processor.h"
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| /qemu/tests/functional/ |
| H A D | test_ppc64_powernv.py | 99 self.wait_for_console_pattern("CPU: " + proc + " generation processor")
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| /qemu/tests/bench/ |
| H A D | atomic64-bench.c | 10 #include "qemu/processor.h"
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| H A D | atomic_add-bench.c | 4 #include "qemu/processor.h"
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| /qemu/include/hw/arm/ |
| H A D | allwinner-h3.h | 22 * processor cores. Features and specifications include DDR2/DDR3 memory,
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| /qemu/target/xtensa/core-dsp3400/ |
| H A D | core-matmap.h | 3 * parameters (CHAL) of the Xtensa processor core configuration.
8 * In the Xtensa processor products released to date, all parameters
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| /qemu/hw/arm/ |
| H A D | raspi.c | 53 FIELD(REV_CODE, PROCESSOR, 12, 4);
83 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); in board_processor_id()
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| /qemu/target/ppc/translate/ |
| H A D | misc-impl.c.inc | 132 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
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