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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN1.td1 //=- AArch64SchedNeoverseN1.td - NeoverseN1 Scheduling Model -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // - "Arm Neoverse N1 Software Optimization Guide"
13 // - https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1
15 //===----------------------------------------------------------------------===//
18 let IssueWidth = 8; // Maximum micro-ops dispatch rate.
19 let MicroOpBufferSize = 128; // NOTE: Copied from Cortex-A76.
22 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
31 //===----------------------------------------------------------------------===//
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H A DAArch64SchedNeoverseN2.td1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 10; // Micro-ops dispatched at a time.
15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
25 //===----------------------------------------------------------------------===//
27 // Instructions are first fetched and then decoded into internal macro-ops
29 // stages. A MOP can be split into two micro-ops further down the pipeline
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H A DAArch64Schedule.td1 //==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
33 def WriteID32 : SchedWrite; // 32-bit Divide
34 def WriteID64 : SchedWrite; // 64-bit Divide
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H A DAArch64SchedNeoverseV2.td1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2
14 //===----------------------------------------------------------------------===//
17 let IssueWidth = 16; // Micro-ops dispatched at a time.
18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
29 //===----------------------------------------------------------------------===//
31 // Instructions are first fetched and then decoded into internal macro-ops
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H A DAArch64SchedNeoverseV1.td1 //=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // - "Arm Neoverse V1 Software Optimization Guide"
13 // - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing"
14 …//community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-plat…
15 // - "Neoverse V1"
19 //===----------------------------------------------------------------------===//
22 let IssueWidth = 15; // Maximum micro-ops dispatch rate.
23 let MicroOpBufferSize = 256; // Micro-op re-order buffer.
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H A DAArch64SchedA55.td1 //==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the ARM Cortex-A55 processors. Note
10 // that this schedule is currently used as the default for -mcpu=generic. As a
12 // Cortex-A55, instead aiming to be a good compromise between different cpus.
14 //===----------------------------------------------------------------------===//
16 // ===---------------------------------------------------------------------===//
17 // The following definitions describe the per-operand machine model.
20 // Cortex-A55 machine model for scheduling and other instruction cost heuristics.
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H A DAArch64SchedThunderX2T99.td1 //=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 let IssueWidth = 4; // 4 micro-ops dispatched at a time.
20 let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
23 // Determined via a mix of micro-arch details and experimentation.
65 // Integer divide and multiply micro-ops only on port 1.
68 // Branch micro-ops only on port 2.
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H A DAArch64SchedThunderX3T110.td1 //=- AArch64SchedThunderX3T110.td - Marvell ThunderX3 T110 ---*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 let IssueWidth = 4; // 4 micro-ops dispatched at a time.
19 let MicroOpBufferSize = 70; // 70 entries in micro-op re-order buffer.
22 // Determined via a mix of micro-arch details and experimentation.
75 // Integer divide/mulhi micro-ops only on port I1.
78 // Branch micro-ops on ports I2/I3.
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H A DAArch64SchedA510.td1 //==- AArch64SchedCortexA510.td - ARM Cortex-A510 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the ARM Cortex-A510 processor.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the per-operand machine model.
17 // Cortex-A510 machine model for scheduling and other instruction cost heuristics.
19 let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor
20 let IssueWidth = 3; // It dual-issues under most circumstances
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H A DAArch64SchedTSV110.td1 //==- AArch64SchedTSV110.td - Huawei TSV110 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // ===---------------------------------------------------------------------===//
15 // The following definitions describe the simpler per-operand machine model.
20 let IssueWidth = 4; // 4 micro-ops dispatched per cycle.
21 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
34 // which has 8 pipelines, each with its own queue where micro-ops wait for
35 // their operands and issue out-of-order to one of eight execution pipelines.
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H A DAArch64SchedA64FX.td1 //=- AArch64SchedA64FX.td - Fujitsu A64FX Scheduling Defs -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 6; // 6 micro-ops dispatched at a time.
15 let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
18 // Determined via a mix of micro-arch details and experimentation.
550 //===----------------------------------------------------------------------===//
553 //---
555 //---
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1 //=- ARMScheduleA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for ARM Cortex-A57 to support
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // The Cortex-A57 is a traditional superscalar microprocessor with a
17 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
18 // much wider out-of-order issue stage, this produced a need to carefully
19 // schedule micro-ops so that all three decoded each cycle are successfully
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H A DARMScheduleSwift.td1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
31 // FIXME: Do we need to model the fact that uses of r15 in a micro-op force it
34 // FIXME: Better model the microcode stages of multiply instructions, especially
37 // FIXME: Model non-pipelined nature of FP div / sqrt unit.
41 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
52 def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>;
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H A DARMScheduleM7.td1 //=- ARMScheduleM7.td - ARM Cortex-M7 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
11 //===----------------------------------------------------------------------===//
15 let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
16 let LoadLatency = 2; // Best case for load-use case.
24 //===--------------------------------------------------------------------===//
25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
53 //===---------------------------------------------------------------------===//
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H A DARMISelLowering.h1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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/src/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx8qxp-dc-fetchunit.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit
15 planes in Blit Engines, and comprises the following built-in functions to
18 +---------X-----------------------------------------+
21 | +---------+ |
25 | +---------+ |
28 | +---------+ |
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H A Dfsl,imx8qxp-dc-matrix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-matrix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The unit supports linear color transformation, alpha pre-multiply and
14 - Liu Ying <victor.liu@nxp.com>
18 const: fsl,imx8qxp-dc-matrix
24 reg-names:
26 - const: cfg # matrix in display engine
27 - items: # matrix in pixel engine
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/src/contrib/lutok/
H A Doperations_test.cpp33 #include <atf-c++.hpp>
45 /// \pre stack(-2) The first summand.
46 /// \pre stack(-1) The second summand.
47 /// \post stack(-1) The result of the sum.
55 state.push_integer(state.to_integer(-1) + state.to_integer(-2)); in hook_add()
62 /// \pre stack(-2) The first factor.
63 /// \pre stack(-1) The second factor.
64 /// \post stack(-1) The product.
72 state.push_integer(state.to_integer(-1) * state.to_integer(-2)); in hook_multiply()
89 ATF_REQUIRE(state.to_boolean(-1)); in ATF_TEST_CASE_BODY()
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/src/contrib/jemalloc/include/jemalloc/internal/
H A Ddiv.h10 * We do some pre-computation to do this more quickly than a CPU division
27 assert(n <= (uint32_t)-1); in div_compute()
29 * This generates, e.g. mov; imul; shr on x86-64. On a 32-bit machine, in div_compute()
31 * appropriate "get the high 32 bits of the result of a multiply" (e.g. in div_compute()
34 size_t i = ((uint64_t)n * (uint64_t)div_info->magic) >> 32; in div_compute()
36 assert(i * div_info->d == n); in div_compute()
/src/sys/contrib/openzfs/module/zstd/lib/common/
H A Dxxhash.h1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only
3 * xxHash - Extremely Fast Hash algorithm
5 * Copyright (c) Yann Collet - Meta Platforms, Inc
7 * This source code is licensed under both the BSD-style license (found in the
10 * You may select, at your option, one of the above-listed licenses.
26 * xxHash is an extremely fast non-cryptographic hash algorithm, working at RAM speed
31 * - Classic 32-bit hash function. Simple, compact, and runs on almost all
32 * 32-bit and 64-bit systems.
34 * - Classic 64-bit adaptation of XXH32. Just as simple, and runs well on most
35 * 64-bit systems (but _not_ 32-bit systems).
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/src/contrib/llvm-project/llvm/include/llvm/Support/
H A DScaledNumber.h1 //===- llvm/Support/ScaledNumber.h - Support for scaled numbers -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // numbers -- in particular, pairs of integers where one represents digits and
13 // certain cost metrics that need simple, integer-like semantics that are easy
16 // These might remind you of soft-floats. If you want one of those, you're in
19 //===----------------------------------------------------------------------===//
39 const int32_t MinScale = -16382;
50 /// \pre adding 1 to \c Scale will not overflow INT16_MAX.
59 return std::make_pair(DigitsT(1) << (getWidth<DigitsT>() - 1), Scale + 1); in getRounded()
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/src/sys/dev/videomode/
H A Dvesagtf.c3 /*-
43 * This has required the use of 64-bit integers in a few places, but
89 * Copyright (c) 1994, 1995, 1996 - Video Electronics Standards
120 * surrounding the addressable video); on most non-overscan type
172 * #define C_PRIME (((C - J) * K/256.0) + J)
180 #define C_PRIME256(p) (((p->C - p->J) * p->K) + (p->J * 256))
181 #define M_PRIME256(p) (p->K * p->M)
186 * print_value() - print the result of the named computation; this is
195 printf("%2d: %-27s: %u\n", n, name, val); in print_value()
202 * vert_refresh() - as defined by the GTF Timing Standard, compute the
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/src/sys/dev/qat/qat_api/include/lac/
H A Dcpa_cy_ecdsa.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
52 * For optimal performance all data buffers SHOULD be 8-byte aligned.
100 * For optimal performance all data buffers SHOULD be 8-byte aligned.
143 * For optimal performance all data buffers SHOULD be 8-byte aligned.
195 * For optimal performance all data buffers SHOULD be 8-byte aligned.
347 * @param[in] pCallbackTag User-supplied value to help identify request.
358 * @pre
398 * @param[in] pCallbackTag User-supplied value to help identify request.
410 * @pre
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/src/contrib/llvm-project/llvm/lib/Support/
H A Dxxhash.cpp2 * xxHash - Extremely Fast Hash algorithm
3 * Copyright (C) 2012-2023, Yann Collet
5 * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
31 * - xxHash homepage: http://www.xxhash.com
32 * - xxHash source repository : https://github.com/Cyan4973/xxHash
67 return (X << R) | (X >> (64 - R)); in rotl64()
111 const unsigned char *const Limit = BEnd - 32; in xxHash64()
115 uint64_t V4 = Seed - PRIME64_1; in xxHash64()
171 // clang-format off
186 // clang-format on
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/src/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddffma.S1 //===----------------------Hexagon builtin routine ------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #define END(TAG) .size TAG,.-TAG
12 // Double Precision Multiply
91 // 0x0100_0000_0000_0000 has EXP of EXPA+EXPB-BIAS
119 ATMP = insert(A,#MANTBITS,#EXPBITS-3)
120 BTMP = insert(B,#MANTBITS,#EXPBITS-3)
139 CTMP = insert(C,#MANTBITS,#EXPBITS-3)
146 P_TMP = cmp.gt(CH,#-1)
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