| /linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
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| D | amdgpu_pll.c | 279 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
283 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
284 * also in DP mode. For DP, a single PPLL can be used for all DP
308 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
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| D | dce_v8_0.c | 2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2149 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2158 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2172 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2183 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2499 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
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| D | dce_v11_0.c | 2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2328 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2331 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2337 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2350 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2359 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2678 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
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| D | atombios_crtc.c | 837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
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| D | dce_v10_0.c | 2228 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2232 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2233 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2234 * monitors a dedicated PPLL must be used. If a particular board has
2259 /* skip PPLL programming if using ext clock */ in dce_v10_0_pick_pll()
2262 /* use the same PPLL for all DP monitors */ in dce_v10_0_pick_pll()
2268 /* use the same PPLL for all monitors with the same clock */ in dce_v10_0_pick_pll()
2282 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v10_0_pick_pll()
2599 /* disable the ppll */ in dce_v10_0_crtc_disable()
2662 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
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| D | dce_v6_0.c | 2133 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2137 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2138 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2139 * monitors a dedicated PPLL must be used. If a particular board has
2157 /* skip PPLL programming if using ext clock */ in dce_v6_0_pick_pll()
2162 /* use the same PPLL for all monitors with the same clock */ in dce_v6_0_pick_pll()
2174 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v6_0_pick_pll()
2488 /* disable the ppll */ in dce_v6_0_crtc_disable()
2552 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
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| D | amdgpu.h | 353 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; member
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| /linux-5.10/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1753 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1757 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1758 * also in DP mode. For DP, a single PPLL can be used for all DP
1787 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1792 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1838 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1842 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1843 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1844 * monitors a dedicated PPLL must be used. If a particular board has
1887 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
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| D | atombios.h | 1545 // 0 means disable PPLL
1552 UCHAR ucCRTC; // Which CRTC uses this Ppll
1565 // 0 means disable PPLL
1572 UCHAR ucCRTC; // Which CRTC uses this Ppll
1612 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1625 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1641 // 0 means disable PPLL/DCPLL.
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1652 // bit[4]= RefClock source for PPLL.
1675 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
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| D | radeon_encoders.c | 59 /* DVO requires 2x ppll clocks depending on tmds chip */ in radeon_encoder_clones()
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| /linux-5.10/drivers/clk/imx/ |
| D | clk-imx35.c | 61 static const char *std_sel[] = {"ppll", "arm"};
65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
118 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
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| /linux-5.10/drivers/clk/rockchip/ |
| D | clk-rk3399.c | 23 ppll, enumerator
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
140 "ppll" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
150 "ppll", "upll", "xin24m" };
210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1405 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1426 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
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| /linux-5.10/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 206 * other ppll params */
209 * other ppll params */
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 21 ppll 2
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| /linux-5.10/include/dt-bindings/clock/ |
| D | xlnx-versal-clk.h | 19 #define PPLL 10 macro
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| /linux-5.10/drivers/video/fbdev/aty/ |
| D | radeon_base.c | 1364 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1376 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1379 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1384 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1391 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1410 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1436 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1825 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
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| D | radeon_pm.c | 1663 /* Restore our "reference" PPLL divider set by firmware in radeon_pm_restore_pixel_pll()
2089 /* PPLL and P2PLL default values & off */ in radeon_reinitialize_M9P()
2206 /* Restore PPLL, spread spectrum & LVDS */ in radeon_reinitialize_M9P()
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| D | radeon_monitor.c | 675 "from PPLL %d\n", in radeon_fixup_panel_info()
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| /linux-5.10/drivers/gpu/drm/amd/include/ |
| D | atombios.h | 1820 // 0 means disable PPLL
1827 UCHAR ucCRTC; // Which CRTC uses this Ppll
1840 // 0 means disable PPLL
1847 UCHAR ucCRTC; // Which CRTC uses this Ppll
1887 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1917 // 0 means disable PPLL/DCPLL.
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1928 // bit[4]= RefClock source for PPLL.
1951 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
[all …]
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| D | atomfirmware.h | 3244 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
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| /linux-5.10/arch/mips/pci/ |
| D | pci-mt7620.c | 243 dev_err(&pdev->dev, "MT7620 PPLL unlock\n"); in mt7620_pci_hw_init()
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| /linux-5.10/drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table.c | 1088 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to in set_pixel_clock_v6()
1165 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to in set_pixel_clock_v7()
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| D | command_table2.c | 389 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to in set_pixel_clock_v7()
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| /linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 334 * So calculate PPLL FB and fractional FB divider in calculate_pixel_clock_pll_dividers()
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