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/linux-5.10/Documentation/livepatch/
Dcallbacks.rst5 Livepatch (un)patch-callbacks provide a mechanism for livepatch modules
10 - Safe updates to global data
12 - "Patches" to init and probe functions
14 - Patching otherwise unpatchable code (i.e. assembly)
25 - Module init/exit code doesn't run when disabling and re-enabling a
28 - A module notifier can't stop a to-be-patched module from loading.
39 * Pre-patch
40 - before a klp_object is patched
42 * Post-patch
43 - after a klp_object has been patched and is active
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dgm200.c34 struct nvkm_device *device = init->base.subdev.device; in pmu_code()
35 struct nvkm_bios *bios = device->bios; in pmu_code()
54 struct nvkm_device *device = init->base.subdev.device; in pmu_data()
55 struct nvkm_bios *bios = device->bios; in pmu_data()
66 struct nvkm_device *device = init->base.subdev.device; in pmu_args()
75 struct nvkm_device *device = init->base.subdev.device; in pmu_exec()
82 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
85 struct nvkm_subdev *subdev = &init->base.subdev; in pmu_load()
86 struct nvkm_bios *bios = subdev->device->bios; in pmu_load()
90 return -EINVAL; in pmu_load()
[all …]
Dbase.c32 if (init->func->mmio) in nvkm_devinit_mmio()
33 addr = init->func->mmio(init, addr); in nvkm_devinit_mmio()
40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
46 if (init->func->meminit) in nvkm_devinit_meminit()
47 init->func->meminit(init); in nvkm_devinit_meminit()
53 if (init && init->func->disable) in nvkm_devinit_disable()
54 return init->func->disable(init); in nvkm_devinit_disable()
62 if (init && init->func->post) in nvkm_devinit_post()
63 ret = init->func->post(init, init->post); in nvkm_devinit_post()
74 init->post = true; in nvkm_devinit_fini()
[all …]
Dnv50.c37 struct nvkm_subdev *subdev = &init->subdev; in nv50_devinit_pll_set()
38 struct nvkm_device *device = subdev->device; in nv50_devinit_pll_set()
39 struct nvkm_bios *bios = device->bios; in nv50_devinit_pll_set()
53 return -EINVAL; in nv50_devinit_pll_set()
83 struct nvkm_device *device = init->subdev.device; in nv50_devinit_disable()
96 struct nvkm_subdev *subdev = &base->subdev; in nv50_devinit_preinit()
97 struct nvkm_device *device = subdev->device; in nv50_devinit_preinit()
101 * missing, assume it's a secondary gpu which requires post in nv50_devinit_preinit()
103 if (!base->post) { in nv50_devinit_preinit()
106 base->post = true; in nv50_devinit_preinit()
[all …]
Dtu102.c31 struct nvkm_subdev *subdev = &init->subdev; in tu102_devinit_pll_set()
32 struct nvkm_device *device = subdev->device; in tu102_devinit_pll_set()
34 int head = type - PLL_VPLL0; in tu102_devinit_pll_set()
38 ret = nvbios_pll_parse(device->bios, type, &info); in tu102_devinit_pll_set()
61 ret = -EINVAL; in tu102_devinit_pll_set()
69 tu102_devinit_post(struct nvkm_devinit *base, bool post) in tu102_devinit_post() argument
72 gm200_devinit_preos(init, post); in tu102_devinit_post()
79 .post = tu102_devinit_post,
/linux-5.10/tools/testing/selftests/livepatch/
Dtest-callbacks.sh2 # SPDX-License-Identifier: GPL-2.0
19 # - On livepatch enable, before the livepatch transition starts,
20 # pre-patch callbacks are executed for vmlinux and $MOD_TARGET (those
22 # according to the klp_patch, their post-patch callbacks run and the
25 # - Similarly, on livepatch disable, pre-patch callbacks run before the
26 # unpatching transition starts. klp_objects are reverted, post-patch
43 $MOD_LIVEPATCH: pre_patch_callback: $MOD_TARGET -> [MODULE_STATE_LIVE] Normal state
47 $MOD_LIVEPATCH: post_patch_callback: $MOD_TARGET -> [MODULE_STATE_LIVE] Normal state
52 $MOD_LIVEPATCH: pre_unpatch_callback: $MOD_TARGET -> [MODULE_STATE_LIVE] Normal state
56 $MOD_LIVEPATCH: post_unpatch_callback: $MOD_TARGET -> [MODULE_STATE_LIVE] Normal state
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/linux-5.10/drivers/media/i2c/cx25840/
Dcx25840-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <media/v4l2-common.h>
9 #include <media/drv-intf/cx25840.h>
11 #include "cx25840-core.h"
35 if (state->aud_input != CX25840_AUDIO_SERIAL) { in cx25840_set_audclk_freq()
39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
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/linux-5.10/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt1 Status: Unstable - ABI compatibility may be broken in the future
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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/linux-5.10/drivers/clk/qcom/
Dclk-alpha-pll.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
57 * struct clk_alpha_pll - phase locked loop (PLL)
78 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
81 * @width: width of post-divider
82 * @post_div_shift: shift to differentiate between odd & even post-divider
83 * @post_div_table: table with PLL odd and even post-divider settings
84 * @num_post_div: Number of PLL post-divider settings
/linux-5.10/tools/testing/selftests/drivers/net/netdevsim/
Ddevlink.sh2 # SPDX-License-Identifier: GPL-2.0
60 cmd_jq "devlink dev param show $DL_HANDLE name $name -j" \
105 check_value max_macs post-set 16 32
106 check_value test1 post-set false Y
110 check_value max_macs post-reload 16 16
111 check_value test1 post-reload false N
121 size=$(devlink region show $DL_HANDLE/$name -j | jq -e -r '.[][].size')
123 [ $size -eq 32768 ]
134 count=$(devlink region show $DL_HANDLE/$name -j | jq -e -r '.[][].snapshot | length')
135 [ $count -eq $expected_count ]
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/linux-5.10/drivers/video/fbdev/matrox/
Dmatroxfb_misc.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 unsigned int* in, unsigned int* feed, unsigned int* post);
13 unsigned int *post) in PLL_calcclock() argument
15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from cx25840-audio.c
11 #include "cx18-driver.h"
15 struct cx18_av_state *state = &cx->av_state; in set_audclk_freq()
18 return -EINVAL; in set_audclk_freq()
31 * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80 in set_audclk_freq()
34 * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83 in set_audclk_freq()
56 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) { in set_audclk_freq()
60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
[all …]
/linux-5.10/tools/testing/selftests/tc-testing/creating-plugins/
DAddingPlugins.txt1 tdc - Adding plugins for tdc
3 Author: Brenda J. Butler - bjb@mojatatu.com
6 --------------
9 There are some examples in plugin-lib.
14 - adding commands to be run before and/or after the test suite
15 - adding commands to be run before and/or after the test cases
16 - adding commands to be run before and/or after the execute phase of the test cases
17 - ability to alter the command to be run in any phase:
18 pre (the pre-suite stage)
23 post (the post-suite stage)
[all …]
/linux-5.10/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
40 * - Render Target Cache Flush Enable ([12] of DW1)
[all …]
/linux-5.10/sound/core/
Dpcm_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
22 struct snd_pcm_runtime *runtime = substream->runtime; in snd_pcm_timer_resolution_change()
25 rate = runtime->rate; in snd_pcm_timer_resolution_change()
31 fsize = runtime->period_size; in snd_pcm_timer_resolution_change()
37 post = 1; in snd_pcm_timer_resolution_change()
40 post *= 2; in snd_pcm_timer_resolution_change()
43 pcm_err(substream->pcm, in snd_pcm_timer_resolution_change()
45 runtime->rate, runtime->period_size); in snd_pcm_timer_resolution_change()
46 runtime->timer_resolution = -1; in snd_pcm_timer_resolution_change()
[all …]
/linux-5.10/drivers/mmc/core/
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
129 * mmc_claim_host - exclusively claim a host
144 * mmc_pre_req - Prepare for a new request
154 if (host->ops->pre_req) in mmc_pre_req()
155 host->ops->pre_req(host, mrq); in mmc_pre_req()
159 * mmc_post_req - Post process a completed request
160 * @host: MMC host to post process command
161 * @mrq: MMC request to post process for
164 * Let the host post process a completed request. Post processing of
170 if (host->ops->post_req) in mmc_post_req()
[all …]
/linux-5.10/arch/x86/include/asm/
Dparavirt_types.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define CLBR_ANY ((1 << 4) - 1)
30 #define CLBR_ANY ((1 << 9) - 1)
46 #include <asm/nospec-branch.h>
61 * Wrapper type for pointers to code which uses the non-standard
153 * read sets err to 0 or -EIO. write returns 0 or -EIO.
161 * Switch to usermode gs and return to 64-bit usermode using
162 * sysret. Only used in 64-bit kernels to return to 64-bit
226 /* Hooks for allocating and freeing a pagetable top-level */
337 " .byte 772b-771b\n" \
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/linux-5.10/drivers/infiniband/hw/qedr/
Dqedr_roce_cm.c2 * Copyright (c) 2015-2016 QLogic Corporation
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
32 #include <linux/dma-mapping.h>
50 #include <rdma/qedr-abi.h>
55 info->gsi_cons = (info->gsi_cons + 1) % info->max_wr; in qedr_inc_sw_gsi_cons()
61 dev->gsi_qp_created = 1; in qedr_store_gsi_qp_cq()
62 dev->gsi_sqcq = get_qedr_cq(attrs->send_cq); in qedr_store_gsi_qp_cq()
63 dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq); in qedr_store_gsi_qp_cq()
64 dev->gsi_qp = qp; in qedr_store_gsi_qp_cq()
[all …]
/linux-5.10/drivers/infiniband/hw/i40iw/
Di40iw_uk.c3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 * i40iw_nop_1 - insert a nop wqe and move head. no post work
54 if (!qp->sq_ring.head) in i40iw_nop_1()
57 wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring); in i40iw_nop_1()
58 wqe = qp->sq_base[wqe_idx].elem; in i40iw_nop_1()
60 qp->sq_wrtrk_array[wqe_idx].wqe_size = I40IW_QP_WQE_MIN_SIZE; in i40iw_nop_1()
62 peek_head = (qp->sq_ring.head + 1) % qp->sq_ring.size; in i40iw_nop_1()
63 wqe_0 = qp->sq_base[peek_head].elem; in i40iw_nop_1()
[all …]
/linux-5.10/Documentation/ABI/testing/
Dconfigfs-most9 # mount -t configfs none /sys/kernel/config/
22 configure the sub-buffer size for this channel
60 configuration, the creation is post-poned until
77 configure the sub-buffer size for this channel
115 configuration, the creation is post-poned until
132 configure the sub-buffer size for this channel
170 configuration, the creation is post-poned until
198 configure the sub-buffer size for this channel
236 configuration, the creation is post-poned until
/linux-5.10/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
39 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
68 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
[all …]
/linux-5.10/drivers/clk/ingenic/
Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
39 * their encoded values in the PLL control register, or -1 for
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/linux-5.10/tools/testing/selftests/tc-testing/
DREADME1 tdc - Linux Traffic Control (tc) unit testing suite
3 Author: Lucas Bates - lucasb@mojatatu.com
10 ------------
24 * All tc-related features being tested must be built in or available as
26 ./tdc.py -c
30 teardown commands - which includes not being able to run a test simply
32 handled in a future version - the current workaround is to run the tests
37 --------------
44 using the -p option when running tdc:
45 ./tdc.py -p /path/to/tc
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/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
74 * @post_div: post divider
80 * Calculate feedback and reference divider for a given post divider. Makes
87 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
102 * amdgpu_pll_compute - compute PLL paramaters
122 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
132 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
133 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
135 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
[all …]

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