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Searched +full:pmu +full:- +full:sram (Results 1 – 25 of 71) sorted by relevance

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/linux-5.10/arch/arm/mach-rockchip/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
35 static struct regmap *pmu; variable
43 ret = regmap_read(pmu, PMU_PWRDN_ST, &val); in pmu_power_domain_is_on()
57 np = dev->of_node; in rockchip_get_core_reset()
85 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); in pmu_set_power_domain()
92 ret = -1; in pmu_set_power_domain()
120 if (!sram_base_addr || (has_pmu && !pmu)) { in rockchip_boot_secondary()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
[all …]
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Tony Xie <tony.xie@rock-chips.com>
55 rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8); in rk3288_config_bootdata()
99 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR in rk3288_slp_mode_set()
100 * PCLK_WDT_GATE - disable WDT during suspend. in rk3288_slp_mode_set()
232 pr_err("%s: could not find pmu regmap\n", __func__); in rk3288_suspend_init()
237 "rockchip,rk3288-sgrf"); in rk3288_suspend_init()
244 "rockchip,rk3288-grf"); in rk3288_suspend_init()
251 "rockchip,rk3288-pmu-sram"); in rk3288_suspend_init()
254 return -ENODEV; in rk3288_suspend_init()
[all …]
/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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/linux-5.10/arch/arm/mach-meson/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
36 static struct regmap *pmu; variable
66 /* SMP SRAM */ in meson_smp_prepare_cpus()
69 pr_err("Missing SRAM node\n"); in meson_smp_prepare_cpus()
75 pr_err("Couldn't map SRAM registers\n"); in meson_smp_prepare_cpus()
79 /* PMU */ in meson_smp_prepare_cpus()
80 pmu = syscon_regmap_lookup_by_compatible(pmu_compatible); in meson_smp_prepare_cpus()
81 if (IS_ERR(pmu)) { in meson_smp_prepare_cpus()
[all …]
/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-tcon-top.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/thermal/thermal.h>
[all …]
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/linux-5.10/arch/arm/boot/dts/
Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
[all …]
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-816000000 {
[all …]
Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
[all …]
Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
[all …]
Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
[all …]
Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
[all …]
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
/linux-5.10/arch/mips/boot/dts/lantiq/
Ddanube.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "lantiq,biu", "simple-bus";
21 #interrupt-cells = <1>;
22 interrupt-controller;
33 sram@1f000000 {
34 #address-cells = <1>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/power/
Drockchip-io-domain.txt1 Rockchip SRAM for IO Voltage Domains:
2 -------------------------------------
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
[all …]
/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/k3.h>
12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/linux-5.10/arch/csky/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
276 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
281 int "Maximum number of CPUs (2-32)"
[all …]
/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/power/meson-gxbb-power.h>
16 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]

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