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/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt65xx.txt3 The Mediatek's Pin controller is used to control SoC pins.
6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
14 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
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/linux-5.10/drivers/pinctrl/nomadik/
Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* pins alternate function */
30 * struct abx500_function - ABx500 pinctrl mux function
42 * struct abx500_pingroup - describes a ABx500 pin group
44 * @pins: an array of discrete physical pins used in this group, taken
45 * from the driver-local pin enumeration space
46 * @num_pins: the number of pins in this group array, i.e. the number of
47 * elements in .pins so we can iterate over that array
48 * @altsetting: the altsetting to apply to all pins in this group to
53 const unsigned int *pins; member
[all …]
Dpinctrl-nomadik.h1 /* SPDX-License-Identifier: GPL-2.0 */
62 * Used to reference an Other alternate-C function.
73 * struct prcm_gpio_altcx - Other alternate-C function
74 * @used: other alternate-C function availability
85 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
87 * @altcx: array of other alternate-C[1-4] functions
95 * struct nmk_function - Nomadik pinctrl mux function
107 * struct nmk_pingroup - describes a Nomadik pin group
109 * @pins: an array of discrete physical pins used in this group, taken
110 * from the driver-local pin enumeration space
[all …]
/linux-5.10/drivers/pinctrl/tegra/
Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
44 /* argument: Integer, range is HW-dependant */
46 /* argument: Integer, range is HW-dependant */
48 /* argument: Integer, range is HW-dependant */
50 /* argument: Integer, range is HW-dependant */
52 /* argument: Integer, range is HW-dependant */
72 * struct tegra_function - Tegra pinctrl mux function
84 * struct tegra_pingroup - Tegra pin group
86 * @pins An array of pin IDs included in this pin group.
87 * @npins The number of entries in @pins.
[all …]
/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dadv7604.txt3 The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
12 - compatible: Must contain one of the following
13 - "adi,adv7611" for the ADV7611
14 - "adi,adv7612" for the ADV7612
16 - reg: I2C slave addresses
17 The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
19 slave device on the I2C bus. The main address is mandatory, others are
22 - hpd-gpios: References to the GPIOs that control the HDMI hot-plug
23 detection pins, one per HDMI input. The active flag indicates the GPIO
24 level that enables hot-plug detection.
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/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/mt65xx.h>
32 #include "../pinctrl-utils.h"
33 #include "mtk-eint.h"
34 #include "pinctrl-mtk-common.h"
48 * There are two base address for pull related configuration
49 * in mt8135, and different GPIO pins use different base address.
56 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) in mtk_get_regmap()
57 return pctl->regmap2; in mtk_get_regmap()
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/linux-5.10/arch/arm/boot/dts/
Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
12 pinctrl: pin-controller {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
18 pins-are-numbered;
21 gpio-controller;
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Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
Dste-snowball.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "regulator-fixed";
22 regulator-name = "en-3v3-fixed-supply";
23 regulator-min-microvolt = <3300000>;
[all …]
Dstm32f4-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
48 pinctrl: pin-controller {
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include "mt8135-pinfunc.h"
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
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Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
[all …]
/linux-5.10/drivers/pinctrl/spear/
Dpinctrl-spear.h25 * struct spear_pmx_mode - SPEAr pmx mode
41 * struct spear_muxreg - SPEAr mux reg configuration
53 const unsigned *pins; member
84 .pins = __pins, \
91 * struct spear_modemux - SPEAr mode mux configuration
103 * struct spear_pingroup - SPEAr pin group configurations
105 * @pins: array containing pin numbers
106 * @npins: size of pins array
110 * A representation of a group of pins in the SPEAr pin controller. Each group
115 const unsigned *pins; member
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
30 Cross instances are not allowed. The MU instance can only
54 numbered in "aliases" node.
[all …]
/linux-5.10/drivers/pinctrl/stm32/
Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
113 struct stm32_desc_pin *pins; member
145 return function - 1; in stm32_gpio_get_alt()
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
[all …]
/linux-5.10/Documentation/driver-api/gpio/
Dlegacy.rst13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
14 digital signal. They are provided from many kinds of chip, and are familiar
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
25 often have a few such pins to help with pin scarcity on SOCs; and there are
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
[all …]
/linux-5.10/drivers/net/ethernet/freescale/
Dfsl_pq_mdio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
70 * Per-device-type data. Each type of device tree node that we support gets
92 * control interfaces like onchip SERDES and are always tied to the local
93 * mdio pins, which may not be the same as system mdio bus, used for
99 struct fsl_pq_mdio_priv *priv = bus->priv; in fsl_pq_mdio_write()
100 struct fsl_pq_mii __iomem *regs = priv->regs; in fsl_pq_mdio_write()
104 iowrite32be((mii_id << 8) | regnum, &regs->miimadd); in fsl_pq_mdio_write()
107 iowrite32be(value, &regs->miimcon); in fsl_pq_mdio_write()
[all …]
/linux-5.10/drivers/pinctrl/
Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 #include <linux/radix-tree.h>
33 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
39 !ops->get_functions_count || in pinmux_check_ops()
40 !ops->get_function_name || in pinmux_check_ops()
41 !ops->get_function_groups || in pinmux_check_ops()
42 !ops->set_mux) { in pinmux_check_ops()
43 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); in pinmux_check_ops()
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
31 #include <asm-generic/gpio.h>
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
94 * get_pinctrl_dev_from_devname() - look up pin controller device
110 if (!strcmp(dev_name(pctldev->dev), devname)) { in get_pinctrl_dev_from_devname()
[all …]
/linux-5.10/arch/alpha/kernel/
Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
43 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
50 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
56 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
81 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
114 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
115 pr_err("Failed to register isa-cascade interrupt\n"); in common_init_irq()
165 * the on-board NCR and Tulip chips. In the code below, I have used
169 * that's printed on the board. The interrupt pins from the PCI slots
170 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
[all …]
/linux-5.10/drivers/net/can/
Dti_hecc.c7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
38 #include <linux/can/rx-offload.h>
46 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
47 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
52 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
65 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
66 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
70 * The remaining mailboxes are used for reception and are delivered
72 * changed while CAN-bus traffic is being received.
74 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
[all …]
/linux-5.10/arch/mips/include/asm/sgi/
Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
16 * There are 8 DIMM slots on an IP30 system
17 * board, which are grouped into four banks
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
[all …]
/linux-5.10/drivers/usb/serial/
Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
81 /* 0xfe 0x40 are magic values taken from original driver */ in ark3116_write_reg()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
96 /* 0xfe 0xc0 are magic values taken from original driver */ in ark3116_read_reg()
[all …]
/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 cluster0_opp: opp-table-0 {
[all …]

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