xref: /linux/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PD692x0 Power Sourcing Equipment controller
8
9maintainers:
10  - Kory Maincent <kory.maincent@bootlin.com>
11
12allOf:
13  - $ref: pse-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - microchip,pd69200
19      - microchip,pd69210
20      - microchip,pd69220
21
22  reg:
23    maxItems: 1
24
25  vdd-supply:
26    description: Regulator that provides 3.3V VDD power supply.
27
28  vdda-supply:
29    description: Regulator that provides 3.3V VDDA power supply.
30
31  managers:
32    type: object
33    additionalProperties: false
34    description:
35      List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
36      have 4 or 8 physical ports according to the chip version. No need to
37      specify the SPI chip select as it is automatically detected by the
38      PD692x0 PSE controller. The PSE managers have to be described from
39      the lowest chip select to the greatest one, which is the detection
40      behavior of the PD692x0 PSE controller. The PD692x0 support up to
41      12 PSE managers which can expose up to 96 physical ports. All
42      physical ports available on a manager have to be described in the
43      incremental order even if they are not used.
44
45    properties:
46      "#address-cells":
47        const: 1
48
49      "#size-cells":
50        const: 0
51
52    required:
53      - "#address-cells"
54      - "#size-cells"
55
56    patternProperties:
57      "^manager@[0-9a-b]$":
58        type: object
59        additionalProperties: false
60        description:
61          PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
62          ports.
63
64        properties:
65          reg:
66            description:
67              Incremental index of the PSE manager starting from 0, ranging
68              from lowest to highest chip select, up to 11.
69            maxItems: 1
70
71          "#address-cells":
72            const: 1
73
74          "#size-cells":
75            const: 0
76
77          vmain-supply:
78            description: Regulator that provides 44-57V VMAIN power supply.
79
80          vaux5-supply:
81            description: Regulator that provides 5V VAUX5 power supply.
82
83          vaux3p3-supply:
84            description: Regulator that provides 3.3V VAUX3P3 power supply.
85
86        patternProperties:
87          '^port@[0-7]$':
88            type: object
89            additionalProperties: false
90
91            properties:
92              reg:
93                maxItems: 1
94
95            required:
96              - reg
97
98        required:
99          - reg
100          - "#address-cells"
101          - "#size-cells"
102
103required:
104  - compatible
105  - reg
106  - pse-pis
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    i2c {
113      #address-cells = <1>;
114      #size-cells = <0>;
115
116      ethernet-pse@3c {
117        compatible = "microchip,pd69200";
118        reg = <0x3c>;
119
120        managers {
121          #address-cells = <1>;
122          #size-cells = <0>;
123
124          manager0: manager@0 {
125            reg = <0>;
126            #address-cells = <1>;
127            #size-cells = <0>;
128            vmain-supply = <&pse1_supply>;
129
130            phys0: port@0 {
131              reg = <0>;
132            };
133
134            phys1: port@1 {
135              reg = <1>;
136            };
137
138            phys2: port@2 {
139              reg = <2>;
140            };
141
142            phys3: port@3 {
143              reg = <3>;
144            };
145          };
146
147          manager@1 {
148            reg = <1>;
149            #address-cells = <1>;
150            #size-cells = <0>;
151
152            phys4: port@0 {
153              reg = <0>;
154            };
155
156            phys5: port@1 {
157              reg = <1>;
158            };
159
160            phys6: port@2 {
161              reg = <2>;
162            };
163
164            phys7: port@3 {
165              reg = <3>;
166            };
167          };
168        };
169
170        pse-pis {
171          #address-cells = <1>;
172          #size-cells = <0>;
173
174          pse_pi0: pse-pi@0 {
175            reg = <0>;
176            #pse-cells = <0>;
177            pairset-names = "alternative-a", "alternative-b";
178            pairsets = <&phys0>, <&phys1>;
179            polarity-supported = "MDI", "S";
180            vpwr-supply = <&manager0>;
181          };
182          pse_pi1: pse-pi@1 {
183            reg = <1>;
184            #pse-cells = <0>;
185            pairset-names = "alternative-a";
186            pairsets = <&phys2>;
187            polarity-supported = "MDI";
188            vpwr-supply = <&manager0>;
189          };
190        };
191      };
192    };
193