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/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cell
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandr
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H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/linux/drivers/nfc/s3fwrn5/
H A Dphy_common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 struct phy_common *phy = phy_id; in s3fwrn5_phy_set_wake() local
21 mutex_lock(&phy->mutex); in s3fwrn5_phy_set_wake()
22 gpio_set_value(phy->gpio_fw_wak in s3fwrn5_phy_set_wake()
29 s3fwrn5_phy_power_ctrl(struct phy_common * phy,enum s3fwrn5_mode mode) s3fwrn5_phy_power_ctrl() argument
51 s3fwrn5_phy_set_mode(void * phy_id,enum s3fwrn5_mode mode) s3fwrn5_phy_set_mode() argument
53 struct phy_common *phy = phy_id; s3fwrn5_phy_set_mode() local
65 struct phy_common *phy = phy_id; s3fwrn5_phy_get_mode() local
66 enum s3fwrn5_mode mode; s3fwrn5_phy_get_mode() local
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H A Di2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
33 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
35 mutex_lock(&phy->common.mutex); in s3fwrn5_i2c_set_mode()
37 if (s3fwrn5_phy_power_ctrl(&phy in s3fwrn5_i2c_set_mode()
48 struct s3fwrn5_i2c_phy *phy = phy_id; s3fwrn5_i2c_write() local
80 s3fwrn5_i2c_read(struct s3fwrn5_i2c_phy * phy) s3fwrn5_i2c_read() argument
122 struct s3fwrn5_i2c_phy *phy = phy_id; s3fwrn5_i2c_irq_thread_fn() local
151 struct s3fwrn5_i2c_phy *phy = i2c_get_clientdata(client); s3fwrn5_i2c_parse_dt() local
182 struct s3fwrn5_i2c_phy *phy; s3fwrn5_i2c_probe() local
242 struct s3fwrn5_i2c_phy *phy = i2c_get_clientdata(client); s3fwrn5_i2c_remove() local
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/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
15 #include <linux/phy/phy.h>
37 struct phy *phy; member
44 enum phy_mode mode; member
49 if (!data->stg_sysco in phy_usb3_mode_set()
95 phy_kvco_gain_set(struct jh7110_pcie_phy * phy) phy_kvco_gain_set() argument
103 jh7110_pcie_phy_set_mode(struct phy * _phy,enum phy_mode mode,int submode) jh7110_pcie_phy_set_mode() argument
105 struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy); jh7110_pcie_phy_set_mode() local
139 struct jh7110_pcie_phy *phy; jh7110_pcie_phy_probe() local
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/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 HiSilicon Limited.
89 struct mipi_phy_params phy; member
122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy in dsi_calc_phy_rate()
245 dsi_get_phy_params(u32 phy_req_kHz,struct mipi_phy_params * phy) dsi_get_phy_params() argument
331 dsi_set_phy_timer(void __iomem * base,struct mipi_phy_params * phy,u32 lanes) dsi_set_phy_timer() argument
364 dsi_set_mipi_phy(void __iomem * base,struct mipi_phy_params * phy,u32 lanes) dsi_set_mipi_phy() argument
449 dsi_set_mode_timing(void __iomem * base,u32 lane_byte_clk_kHz,struct drm_display_mode * mode,enum mipi_dsi_pixel_format format) dsi_set_mode_timing() argument
540 struct mipi_phy_params *phy = &dsi->phy; dsi_mipi_init() local
541 struct drm_display_mode *mode = &dsi->cur_mode; dsi_mipi_init() local
610 dsi_encoder_phy_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode) dsi_encoder_phy_mode_valid() argument
613 struct mipi_phy_params phy; dsi_encoder_phy_mode_valid() local
641 dsi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode) dsi_encoder_mode_valid() argument
675 dsi_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode) dsi_encoder_mode_set() argument
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixe
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H A Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v
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/linux/drivers/phy/hisilicon/
H A Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
21 #include <dt-bindings/phy/phy
49 struct phy *phy; global() member
50 struct histb_combphy_mode mode; global() member
74 is_mode_fixed(struct histb_combphy_mode * mode) is_mode_fixed() argument
81 struct histb_combphy_mode *mode = &priv->mode; histb_combphy_set_mode() local
106 histb_combphy_init(struct phy * phy) histb_combphy_init() argument
143 histb_combphy_exit(struct phy * phy) histb_combphy_exit() argument
169 struct histb_combphy_mode *mode = &priv->mode; histb_combphy_xlate() local
198 struct histb_combphy_mode *mode; histb_combphy_probe() local
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/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI DP83822 ethernet PHY
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Commo
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H A Dmicrel.txt1 Micrel PHY properties.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-referenc
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/linux/arch/mips/boot/dts/realtek/
H A Dcameo-rtl9302c-2x-rtl8224-2xge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-binding
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/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY drive
182 enum pipe3_mode mode; global() member
207 enum pipe3_mode mode; global() member
300 ti_pipe3_get_dpll_params(struct ti_pipe3 * phy) ti_pipe3_get_dpll_params() argument
323 struct ti_pipe3 *phy = phy_get_drvdata(x); ti_pipe3_power_off() local
342 struct ti_pipe3 *phy = phy_get_drvdata(x); ti_pipe3_power_on() local
387 ti_pipe3_dpll_wait_lock(struct ti_pipe3 * phy) ti_pipe3_dpll_wait_lock() argument
404 ti_pipe3_dpll_program(struct ti_pipe3 * phy) ti_pipe3_dpll_program() argument
443 ti_pipe3_calibrate(struct ti_pipe3 * phy) ti_pipe3_calibrate() argument
499 struct ti_pipe3 *phy = phy_get_drvdata(x); ti_pipe3_init() local
548 struct ti_pipe3 *phy = phy_get_drvdata(x); ti_pipe3_exit() local
603 ti_pipe3_get_clk(struct ti_pipe3 * phy) ti_pipe3_get_clk() argument
670 ti_pipe3_get_sysctrl(struct ti_pipe3 * phy) ti_pipe3_get_sysctrl() argument
748 ti_pipe3_get_tx_rx_base(struct ti_pipe3 * phy) ti_pipe3_get_tx_rx_base() argument
762 ti_pipe3_get_pll_base(struct ti_pipe3 * phy) ti_pipe3_get_pll_base() argument
777 struct ti_pipe3 *phy; ti_pipe3_probe() local
840 struct ti_pipe3 *phy = platform_get_drvdata(pdev); ti_pipe3_remove() local
849 ti_pipe3_enable_clocks(struct ti_pipe3 * phy) ti_pipe3_enable_clocks() argument
890 ti_pipe3_disable_clocks(struct ti_pipe3 * phy) ti_pipe3_disable_clocks() argument
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/linux/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
57 /* mode: RC, EP */
58 int mode; member
64 struct phy *ph member
76 rockchip_p3phy_set_mode(struct phy * phy,enum phy_mode mode,int submode) rockchip_p3phy_set_mode() argument
98 struct phy *phy = priv->phy; rockchip_p3phy_rk3568_init() local
144 u8 mode = RK3588_LANE_AGGREGATION; /* default */ rockchip_p3phy_rk3588_init() local
205 rockchip_p3phy_init(struct phy * phy) rockchip_p3phy_init() argument
228 rockchip_p3phy_exit(struct phy * phy) rockchip_p3phy_exit() argument
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/linux/drivers/phy/amlogic/
H A Dphy-meson-gxl-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 phy_meson_gxl_usb2_init(struct phy * phy) phy_meson_gxl_usb2_init() argument
125 phy_meson_gxl_usb2_exit(struct phy * phy) phy_meson_gxl_usb2_exit() argument
135 phy_meson_gxl_usb2_reset(struct phy * phy) phy_meson_gxl_usb2_reset() argument
152 phy_meson_gxl_usb2_set_mode(struct phy * phy,enum phy_mode mode,int submode) phy_meson_gxl_usb2_set_mode() argument
153 phy_meson_gxl_usb2_set_mode(struct phy * phy,enum phy_mode mode,int submode) phy_meson_gxl_usb2_set_mode() argument
188 phy_meson_gxl_usb2_power_off(struct phy * phy) phy_meson_gxl_usb2_power_off() argument
201 phy_meson_gxl_usb2_power_on(struct phy * phy) phy_meson_gxl_usb2_power_on() argument
238 struct phy *phy; phy_meson_gxl_usb2_probe() local
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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediate
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H A Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <linux/phy/phy.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 6
142 phy_write(struct phy * phy,u32 value,unsigned int reg) phy_write() argument
186 mixel_dphy_config_from_opts(struct phy * phy,struct phy_configure_opts_mipi_dphy * dphy_opts,struct mixel_dphy_cfg * cfg) mixel_dphy_config_from_opts() argument
320 mixel_phy_set_hs_timings(struct phy * phy) mixel_phy_set_hs_timings() argument
333 mixel_dphy_set_pll_params(struct phy * phy) mixel_dphy_set_pll_params() argument
353 mixel_dphy_configure_mipi_dphy(struct phy * phy,union phy_configure_opts * opts) mixel_dphy_configure_mipi_dphy() argument
382 mixel_dphy_configure_lvds_phy(struct phy * phy,union phy_configure_opts * opts) mixel_dphy_configure_lvds_phy() argument
441 mixel_dphy_configure(struct phy * phy,union phy_configure_opts * opts) mixel_dphy_configure() argument
460 mixel_dphy_validate_lvds_phy(struct phy * phy,union phy_configure_opts * opts) mixel_dphy_validate_lvds_phy() argument
486 mixel_dphy_validate(struct phy * phy,enum phy_mode mode,int submode,union phy_configure_opts * opts) mixel_dphy_validate() argument
503 mixel_dphy_init(struct phy * phy) mixel_dphy_init() argument
511 mixel_dphy_exit(struct phy * phy) mixel_dphy_exit() argument
520 mixel_dphy_power_on_mipi_dphy(struct phy * phy) mixel_dphy_power_on_mipi_dphy() argument
539 mixel_dphy_power_on_lvds_phy(struct phy * phy) mixel_dphy_power_on_lvds_phy() argument
565 mixel_dphy_power_on(struct phy * phy) mixel_dphy_power_on() argument
594 mixel_dphy_power_off(struct phy * phy) mixel_dphy_power_off() argument
609 mixel_dphy_set_mode(struct phy * phy,enum phy_mode mode,int submode) mixel_dphy_set_mode() argument
666 struct phy *phy; mixel_dphy_probe() local
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/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-pat
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/linux/arch/powerpc/boot/dts/fsl/
H A Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-typ
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->is in csiphy_routing_cfg_3630()
69 csiphy_routing_cfg_3430(struct isp_csiphy * phy,u32 iface,bool on,bool ccp2_strobe) csiphy_routing_cfg_3430() argument
102 csiphy_routing_cfg(struct isp_csiphy * phy,enum isp_interface_type iface,bool on,bool ccp2_strobe) csiphy_routing_cfg() argument
116 csiphy_power_autoswitch_enable(struct isp_csiphy * phy,bool enable) csiphy_power_autoswitch_enable() argument
129 csiphy_set_power(struct isp_csiphy * phy,u32 power) csiphy_set_power() argument
163 omap3isp_csiphy_config(struct isp_csiphy * phy) omap3isp_csiphy_config() argument
265 omap3isp_csiphy_acquire(struct isp_csiphy * phy,struct media_entity * entity) omap3isp_csiphy_acquire() argument
308 omap3isp_csiphy_release(struct isp_csiphy * phy) omap3isp_csiphy_release() argument
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