per\-queue (full) in projects: linux - OpenGrok search results

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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A D	bnx2x_mfw_req.h	3 * Copyright (c) 2012-2013 Broadcom Corporation 23 /* Maximum number of I/Os per connection / 26 / Maximum number of Logins per port / 34 / Maximum NPIV WWN per port / 69 / Per PCI Function Ethernet Statistics required from the driver / 94 u32 promiscuous_mode; / Promiscuous Mode. non-zero true / 95 u32 txq_size; / TX Descriptors Queue Size / 96 u32 rxq_size; / RX Descriptors Queue Size / 97 / TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll / 99 / RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */ [all …]
/linux/drivers/net/wireless/intel/iwlwifi/mld/
H A D	agg.h	1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / 12 struct iwl_mld_reorder_buffer - per ra/tid/queue reorder buffer 15 * @queue: queue of this reorder buffer 16 * @valid: true if reordering is valid for this queue 21 int queue; member 26 * struct iwl_mld_reorder_buf_entry - reorder buffer entry per-queue/per-seqno 27 * @frames: list of skbs stored. a list is necessary because in an A-MSDU, 28 * all sub-frames share the same sequence number, so they are stored 41 * struct iwl_mld_baid_data - Block Ack session data 47 * @entries_per_queue: number of buffers per queue, this actually gets [all …]
H A D	sta.h	1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / 3 Copyright (C) 2024-2025 Intel Corporation 15 * struct iwl_mld_rxq_dup_data - Duplication detection data, per STA & Rx queue 16 * @last_seq: last sequence per tid. 17 * @last_sub_frame_idx: the index of the last subframe in an A-MSDU. This value 18 * will be zero if the packet is not part of an A-MSDU. 26 * struct iwl_mld_link_sta - link-level station 28 * This represents the link-level sta - the driver level equivalent to the 50 rcu_dereference_check((mld_sta)->link[link_id], \ 51 lockdep_is_held(&mld_sta->mld->wiphy->mtx)) [all …]
/linux/drivers/net/ethernet/fungible/funeth/
H A D	funeth_txrx.h	1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) / 13 / Size of device headers per Tx packet / 16 / Number of gather list entries per Tx descriptor / 40 #define FUNETH_CQE_INFO_OFFSET (FUNETH_CQE_SIZE - sizeof(struct fun_cqe_info)) 55 / Per packet tailroom. Present only for 1-frag packets. / 58 / Per packet headroom for XDP. Preferred over XDP_PACKET_HEADROOM to 59 * accommodate two packets per buffer for 4K pages and 1500B MTUs. 63 /* Initialization state of a queue. / 65 FUN_QSTATE_DESTROYED, / what queue? / 80 struct funeth_txq_stats { / per Tx queue SW counters */ [all …]
/linux/include/net/
H A D	netdev_queues.h	1 /* SPDX-License-Identifier: GPL-2.0 / 8 struct netdev_config - queue-related configuration for a netdev 65 * struct netdev_stat_ops - netdev ops for fine grained stats 66 * @get_queue_stats_rx: get stats for a given Rx queue 67 * @get_queue_stats_tx: get stats for a given Tx queue 71 * on entry (specifically they are not zero-initialized). Drivers should 75 * Queue objects are not necessarily persistent, and only currently active 76 * queues are queried by the per-queue callbacks. This means that per-queue 83 * is issued to collect the delta, and then a series of per-queue callbacks. 85 * at the device level, meaning that unlike in queue callbacks, setting [all …]
/linux/drivers/media/platform/ti/omap3isp/
H A D	ispvideo.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 5 TI OMAP3 ISP - Generic video node 7 * Copyright (C) 2009-2010 Nokia Corporation 16 #include <linux/v4l2-mediabus.h> 17 #include <media/media-entity.h> 18 #include <media/v4l2-dev.h> 19 #include <media/v4l2-fh.h> 20 #include <media/videobuf2-v4l2.h> 31 * struct isp_format_info - ISP media bus format information 38 * shifted to be 8 bits per pixel. =0 if format is not shiftable. [all …]`
/linux/block/
H A D	bfq-iosched.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 12 #include "blk-cgroup-rwstat.h" 29 Soft real-time applications are extremely more latency sensitive 30 * than interactive ones. Over-raise the weight of the former to 38 * per-actuator data. The current value is hopefully a good upper 46 * struct bfq_service_tree - per ioprio_class service tree. 48 * Each service tree represents a B-WF2Q+ scheduler on its own. Each 50 * bfq_service_tree. All the fields are protected by the queue lock 71 * struct bfq_sched_data - multi-class scheduler. 73 * bfq_sched_data is the basic scheduler queue. It supports three [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 29 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 62 …t counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 72 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 82 …nt counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 87 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 92 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Dec… 97 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 29 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 62 …t counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 72 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 82 …nt counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 87 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 92 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Dec… 97 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
H A D	uncore-io.json	53 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 63 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 73 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 83 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 93 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 103 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 373 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 383 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 393 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… 403 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 29 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 62 …t counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Dec… 72 …counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 82 …nt counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MIT… 87 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 92 …counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Dec… 97 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… [all …]
H A D	uncore-io.json	53 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 63 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 73 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 83 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 93 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 103 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 373 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 383 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 393 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… 403 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… [all …]
/linux/Documentation/filesystems/
H A D	inotify.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 Inotify - A Powerful yet Simple File Change Notification System 13 - Deleted obsoleted interface, just refer to manpages for user interface. 29 What is the design decision behind using an-fd-per-instance as opposed to 30 an fd-per-watch? 33 An fd-per-watch quickly consumes more file descriptors than are allowed, 35 select()-able. Yes, root can bump the per-process fd limit and yes, users 38 spaces is thus sensible. The current design is what user-space developers 41 thousand times is silly. If we can implement user-space's preferences 42 cleanly--and we can, the idr layer makes stuff like this trivial--then we [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	uncore-interconnect.json	93 … "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", 98 …memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for pr… 102 "BriefDescription": "Occupancy of the IRP FAF queue.", 107 …"PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processin… 111 "BriefDescription": "FAF allocation -- sent to ADQ", 148 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", 158 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", 168 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", 178 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", 188 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 93 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 102 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 111 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 121 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 130 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 139 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 93 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 102 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 111 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 121 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 130 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 139 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", [all …]
H A D	uncore-io.json	53 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 63 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 73 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 83 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 93 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 103 …. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messa… 343 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 353 …calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using … 363 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… 373 … calculate average queue latency. Multiple ingress buffers can be tracked at a given time using m… [all …]
/linux/drivers/net/wireless/ath/ath5k/
H A D	dma.c	2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 27 * handle queue setup for 5210 chipset (rest are handled on qcu.c). 44 * ath5k_hw_start_rx_dma() - Start DMA receive 55 * ath5k_hw_stop_rx_dma() - Stop DMA receive 70 i--) in ath5k_hw_stop_rx_dma() 77 return i ? 0 : -EBUSY; in ath5k_hw_stop_rx_dma() 81 * ath5k_hw_get_rxdp() - Get RX Descriptor's address 91 * ath5k_hw_set_rxdp() - Set RX Descriptor's address 95 * Returns -EIO if rx is active [all …]
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A D	sta.h	1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / 3 Copyright (C) 2012-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2016 Intel Deutschland GmbH 14 #include "iwl-trans.h" /* for IWL_MAX_TID_COUNT / 15 #include "fw-api.h" / IWL_STATION_COUNT_MAX / 22 DOC: DQA - Dynamic Queue Allocation -introduction 24 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 25 * driver to allow dynamic allocation of queues on-demand, rather than allocate 26 * them statically ahead of time. Ideally, we would like to allocate one queue [all …]
/linux/include/linux/
H A D	workqueue.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 workqueue.h --- work queue handling for Linux. 21 * The first word is the work queue pointer and the flags rolled into 24 #define work_data_bits(work) ((unsigned long )(&(work)->data)) 52 data contains off-queue information when !WORK_STRUCT_PWQ. 61 WORK_OFFQ_FLAG_BITS = WORK_OFFQ_FLAG_END - WORK_OFFQ_FLAG_SHIFT, 67 * When a work item is off queue, the high bits encode off-queue flags 72 WORK_OFFQ_LEFT = BITS_PER_LONG - WORK_OFFQ_POOL_SHIFT, 102 /* Convenience constants - of type 'unsigned long', not 'enum'! */ 104 #define WORK_OFFQ_FLAG_MASK (((1ul << WORK_OFFQ_FLAG_BITS) - 1) << WORK_OFFQ_FLAG_SHIFT) [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 105 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 114 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 122 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", 130 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 138 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 147 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 155 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while … [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 105 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from D… 114 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe… 122 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", 130 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 138 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from M… 147 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", 155 …"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while … [all …]
/linux/drivers/net/wireless/ti/wl18xx/
H A D	wl18xx.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 43 / number of keys requiring extra spare mem-blocks / 63 is short lived, for multi-channel Tx requirements. 72 /* number of packets to queue up for a link in PS / 75 / number of packet to queue up for a suspended link / 78 / Should have less than this number of packets in queue of a slow 83 /* Should have less than this number of packets in queue of a fast 88 /* Should have less than this number of packets in queue of a slow 93 /* Should have less than this number of packets in queue of a fast 102 /* Cumulative counter of released packets per AC */ [all …]
/linux/Documentation/networking/
H A D	scaling.rst	`1 .. SPDX-License-Identifier: GPL-2.0 13 multi-processor systems. 17 - RSS: Receive Side Scaling 18 - RPS: Receive Packet Steering 19 - RFS: Receive Flow Steering 20 - Accelerated Receive Flow Steering 21 - XPS: Transmit Packet Steering 28 (multi-queue). On reception, a NIC can send different packets to different 32 queue, which in turn can be processed by separate CPUs. This mechanism is 33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and [all …]`
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	uncore-interconnect.json	93 … "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", 98 …memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for pr… 102 "BriefDescription": "Occupancy of the IRP FAF queue.", 107 …"PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processin… 111 "BriefDescription": "FAF allocation -- sent to ADQ", 148 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", 158 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", 168 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", 178 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", 188 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", [all …]

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