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/linux-6.8/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
25 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
34 * On RISC-V systems local interrupts are masked or unmasked by writing
36 * on the local hart, these functions can only be called on the hart that
42 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
47 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
53 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow in riscv_intc_irq_eoi()
54 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
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/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
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/linux-6.8/arch/riscv/kernel/
Dkexec_relocate.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
50 * With C-extension, here we get 42 Bytes and the next
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
62 /* IND_DESTINATION entry ? -> save destination address */
69 /* IND_INDIRECTION entry ? -> update next entry ptr (PA) */
77 /* IND_DONE entry ? -> jump to done label */
84 * IND_SOURCE entry ? -> copy page word by word to the
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Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "copy-unaligned.h"
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
37 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
44 /* Per-cpu ISA extensions. */
53 * riscv_isa_extension_base() - Get base extension word
69 * __riscv_isa_extension_available() - Check whether given extension
94 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
97 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
103 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_isa_extension_check()
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Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <asm/asm-offsets.h>
36 addi sp, sp, -(PT_SIZE_ON_STACK)
46 addi sp, sp, -(PT_SIZE_ON_STACK)
53 * Disable user-mode memory access as it should only be set in the
118 * - handle_exception
119 * - ret_from_fork
153 * different hart contexts. We can't actually save and restore a load
154 * reservation, so instead here we clear any existing reservation --
161 * forward branch around an SC -- which is how we implement CAS. As a
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/linux-6.8/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/linux-6.8/Documentation/arch/riscv/
Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux-6.8/scripts/gdb/linux/
Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
30 if tid > (0x100000000 - MAX_CPUS - 2):
31 return 0x100000000 - tid - 2
40 if cpu == -1:
81 entry = -1
133 super(LxCpus, self).__init__("lx-cpus", gdb.COMMAND_DATA)
146 """Return per-cpu variable.
148 $lx_per_cpu("VAR"[, CPU]): Return the per-cpu variable called VAR for the
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/linux-6.8/drivers/cpuidle/
Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
51 data->available = true; in sbi_set_domain_state()
52 data->state = state; in sbi_set_domain_state()
59 return data->state; in sbi_get_domain_state()
66 data->available = false; in sbi_clear_domain_state()
73 return data->available; in sbi_is_domain_state_available()
114 u32 *states = data->states; in __sbi_enter_domain_idle_state()
115 struct device *pd_dev = data->dev; in __sbi_enter_domain_idle_state()
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/linux-6.8/Documentation/timers/
Dhighres.rst8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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/linux-6.8/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
177 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
184 depends on $(cc-option,-fpatchable-function-entry=8)
187 def_bool $(cc-option,-fsanitize=shadow-call-stack)
188 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
189 depends on $(ld-option,--no-relax-gp)
193 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
196 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
200 # https://github.com/llvm/llvm-project/commit/1df5ea29b43690b6622db2cad7b745607ca4de6a
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/linux-6.8/arch/riscv/kvm/
Daia.c1 // SPDX-License-Identifier: GPL-2.0
38 raw_spin_lock_irqsave(&hgctrl->lock, flags); in aia_find_hgei()
40 hgei = -1; in aia_find_hgei()
42 if (hgctrl->owners[i] == owner) { in aia_find_hgei()
48 raw_spin_unlock_irqrestore(&hgctrl->lock, flags); in aia_find_hgei()
71 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts()
77 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts()
78 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts()
79 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts()
81 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
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/linux-6.8/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/linux-6.8/Documentation/RCU/
DRTFP.txt4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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/linux-6.8/include/acpi/
Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
6 * Copyright (C) 2000 - 2023, Intel Corp.
51 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
59 * All tables must be byte-packed to match the ACPI specification, since
69 * essentially useless for dealing with packed data in on-disk formats or
78 * AEST - Arm Error Source Table
89 /* Common Subtable header - one per Node Structure (Subtable) */
246 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
266 * APMT - ARM Performance Monitoring Unit Table
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/linux-6.8/drivers/platform/x86/
Dwmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ACPI-WMI mapping driver
5 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>
9 * Copyright (c) 2001-2007 Anton Altaparmakov
12 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:
37 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");
93 "05901221-D566-11D1-B2F0-00A0C9062910", /* wmi-bmof */
94 "8A42EA14-4F2A-FD45-6422-0087F7A7E608", /* dell-wmi-ddv */
95 "44FADEB1-B204-40F2-8581-394BBDC1B651", /* intel-wmi-sbl-fw-update */
96 "86CCFD48-205E-4A77-9C48-2021CBEDE341", /* intel-wmi-thunderbolt */
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/linux-6.8/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
38 One pattern per line. Multiple F: lines acceptable.
46 N: [^a-z]tegra all files whose path contains tegra
48 One pattern per line. Multiple N: lines acceptable.
61 One regex pattern per line. Multiple K: lines acceptable.
64 ----------------
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