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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-pic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson PCH PIC Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson LS7A family of PCH for
14 transforming interrupts from on-chip devices into HyperTransport vectorized
19 const: loongson,pch-pic-1.0
22 maxItems: 1
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Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
17 interrupts from PCH PIC connected on HyperTransport bus.
21 const: loongson,htpic-1.0
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/linux-5.10/drivers/irqchip/
Dirq-loongson-pch-pic.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH PIC support
7 #define pr_fmt(fmt) "pch-pic: " fmt
46 void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4; in pch_pic_bitset()
48 raw_spin_lock(&priv->pic_lock); in pch_pic_bitset()
52 raw_spin_unlock(&priv->pic_lock); in pch_pic_bitset()
58 void __iomem *addr = priv->base + offset + PIC_REG_IDX(bit) * 4; in pch_pic_bitclr()
60 raw_spin_lock(&priv->pic_lock); in pch_pic_bitclr()
64 raw_spin_unlock(&priv->pic_lock); in pch_pic_bitclr()
71 pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq); in pch_pic_mask_irq()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 default 1
216 bool "J-Core integrated AIC" if COMPILE_TEST
220 Support for the J-Core integrated AIC.
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 tristate "TS-4800 IRQ controller"
279 Support for the TS-4800 FPGA IRQ controller
442 bool "C-SKY Multi Processor Interrupt Controller"
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/linux-5.10/arch/mips/boot/dts/loongson/
Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 pch: bus@10000000 { label
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 { label
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
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/linux-5.10/drivers/pci/
Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
62 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
63 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
64 (f->vendor == dev->vendor || in pci_do_fixups()
65 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
66 (f->device == dev->device || in pci_do_fixups()
67 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
70 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
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/linux-5.10/arch/x86/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "64-bit kernel" if "$(ARCH)" = "x86"
7 Say yes to build a 64-bit kernel - formerly known as x86_64
8 Say no to build a 32-bit kernel - formerly known as i386
13 # Options that are inherently 32-bit kernel only:
25 # Options that are inherently 64-bit kernel only:
49 # ported to 32-bit as well. )
252 default "elf32-i386" if X86_32
253 default "elf64-x86-64" if X86_64
375 default $(success,$(srctree)/scripts/gcc-x86_64-has-stack-protector.sh $(CC)) if 64BIT
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/linux-5.10/
DMAINTAINERS9 -------------------------
11 1. Always *test* your changes, however small, on at least 4 or
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
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