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Searched +full:otp +full:- +full:1 (Results 1 – 16 of 16) sorted by relevance

/qemu/hw/nvram/
H A Dnpcm7xx_otp.c2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
30 /* 32-bit register indices. */
45 #define FST_RDST BIT(1)
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
84 result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4; in ecc_encode_nibble()
85 result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5; in ecc_encode_nibble()
86 result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6; in ecc_encode_nibble()
87 result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7; in ecc_encode_nibble()
96 uint8_t *dst = &s->array[offset]; in npcm7xx_otp_array_write()
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H A Dbcm2835_otp.c2 * BCM2835 One-Time Programmable (OTP) Memory
4 * The OTP implementation is mostly a stub except for the OTP rows
7 * The OTP registers are unimplemented due to lack of documentation.
11 * SPDX-License-Identifier: MIT
19 /* OTP rows are 1-indexed */
22 assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1); in bcm2835_otp_get_row()
24 return s->otp_rows[row - 1]; in bcm2835_otp_get_row()
30 assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1); in bcm2835_otp_set_row()
32 /* Real OTP rows work as e-fuses */ in bcm2835_otp_set_row()
33 s->otp_rows[row - 1] |= value; in bcm2835_otp_set_row()
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/qemu/hw/misc/
H A Dbcm2835_property.c5 * See the COPYING file in the top-level directory.
11 #include "hw/qdev-properties.h"
15 #include "hw/arm/raspberrypi-fw-defs.h"
24 /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface */
35 BCM2835FBConfig fbconfig = s->fbdev->config; in bcm2835_property_mbox_push()
40 s->addr = value; in bcm2835_property_mbox_push()
42 tot_len = ldl_le_phys(&s->dma_as, value); in bcm2835_property_mbox_push()
45 value = s->addr + 8; in bcm2835_property_mbox_push()
46 while (value + 8 <= s->addr + tot_len) { in bcm2835_property_mbox_push()
47 uint32_t tag = ldl_le_phys(&s->dma_as, value); in bcm2835_property_mbox_push()
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H A Dsifive_u_otp.c2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
6 * Simple model of the OTP to emulate register reads made by the SDK BSP
23 #include "hw/qdev-properties.h"
24 #include "hw/qdev-properties-system.h"
26 #include "qemu/error-report.h"
31 #include "system/block-backend.h"
47 return s->pa; in sifive_u_otp_read()
49 return s->paio; in sifive_u_otp_read()
51 return s->pas; in sifive_u_otp_read()
53 return s->pce; in sifive_u_otp_read()
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/qemu/hw/arm/
H A Dbcm2835_peripherals.c9 * See the COPYING file in the top-level directory.
23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ,
28 * while channels 11--14 share one IRQ:
44 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, in create_unimp()
45 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); in create_unimp()
54 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG); in bcm2835_peripherals_init()
57 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL); in bcm2835_peripherals_init()
60 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO); in bcm2835_peripherals_init()
62 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", in bcm2835_peripherals_init()
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H A Dnpcm8xx.c23 #include "hw/char/serial-mm.h"
27 #include "hw/qdev-clock.h"
28 #include "hw/qdev-properties.h"
40 /* OTP fuse array */
84 * Interrupt lines going into the GIC. This does not include internal Cortex-A35
102 NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */
113 NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
120 NPCM8XX_PWM1_IRQ, /* PWM module 1 */
122 NPCM8XX_MFT1_IRQ, /* MFT module 1 */
175 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
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H A Dnpcm7xx.c21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
39 /* OTP key storage and fuse strap array */
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
100 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
111 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
134 NPCM7XX_MFT1_IRQ, /* MFT module 1 */
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/qemu/include/hw/misc/
H A Dsifive_u_otp.h2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
40 #define SIFIVE_U_OTP_PWE_EN (1 << 0)
42 #define SIFIVE_U_OTP_PCE_EN (1 << 0)
44 #define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
46 #define SIFIVE_U_OTP_PTRIM_EN (1 << 0)
55 #define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
H A Dbcm2835_cprman_internals.h6 * SPDX-License-Identifier: GPL-2.0-or-later
15 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
16 #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
17 #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
18 #define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
33 FIELD(CM_PLLA, LOADDSI0, 0, 1)
34 FIELD(CM_PLLA, HOLDDSI0, 1, 1)
35 FIELD(CM_PLLA, LOADCCP2, 2, 1)
36 FIELD(CM_PLLA, HOLDCCP2, 3, 1)
37 FIELD(CM_PLLA, LOADCORE, 4, 1)
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/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
11 * 1) CLINT (Core Level Interruptor)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
92 #define OTP_SERIAL 1
99 uint64_t mem_size = ms->ram_size; in create_fdt()
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
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H A Dsifive_e.c2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
9 * 1) CLINT (Core Level Interruptor)
16 * The OTP ROM and Flash boot code will be emulated in a future version.
33 #include "qemu/error-report.h"
83 if (machine->ram_size != mc->default_ram_size) { in sifive_e_machine_init()
84 char *sz = size_to_str(mc->default_ram_size); in sifive_e_machine_init()
91 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); in sifive_e_machine_init()
92 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in sifive_e_machine_init()
96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
101 if (s->revb) { in sifive_e_machine_init()
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/qemu/docs/system/riscv/
H A Dsifive_u.rst4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
12 * 1 E51 / E31 core
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
20 * 1 GEM Ethernet controller
21 * 1 GPIO controller
22 * 1 One-Time Programmable (OTP) memory with stored serial number
23 * 1 DMA controller
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/qemu/include/hw/arm/
H A Dbcm2835_peripherals.h9 * See the COPYING file in the top-level directory.
20 #include "hw/or-irq.h"
33 #include "hw/usb/hcd-dwc2.h"
40 #define TYPE_BCM_SOC_PERIPHERALS_BASE "bcm-soc-peripherals-base"
43 #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
72 BCM2835SPIState spi[1];
75 BCM2835OTPState otp; member
/qemu/docs/about/
H A Dremoved-features.rst10 --------------------------------------
12 ``-hdachs`` (removed in 2.12)
15 The geometry defined by ``-hdachs c,h,s,t`` should now be specified via
16 ``-device ide-hd,drive=dr,cyls=c,heads=h,secs=s,bios-chs-trans=t``
17 (together with ``-drive if=none,id=dr,...``).
19 ``-net channel`` (removed in 2.12)
22 This option has been replaced by ``-net user,guestfwd=...``.
24 ``-net dump`` (removed in 2.12)
27 ``-net dump[,vlan=n][,file=filename][,len=maxlen]`` has been replaced by
28 ``-object filter-dump,id=id,netdev=dev[,file=filename][,maxlen=maxlen]``.
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/qemu/hw/sd/
H A Dsd.c5 * eMMC emulation defined in "JEDEC Standard No. 84-A43"
9 * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
15 * 1. Redistributions of source code must retain the above copyright
40 #include "system/block-backend.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/qdev-properties-system.h"
47 #include "qemu/error-report.h"
50 #include "qemu/guest-random.h"
52 #include "sdmmc-internal.h"
55 //#define DEBUG_SD 1
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/qemu/tests/data/qobject/
H A Dqdict.txt1 00-INDEX: 333
12 1d: 4096
13 1.Intro: 14968
55 3.Early-stage: 9993
56 3w-9xxx.c: 77318
57 3w-9xxx.h: 26357
58 3w-xxxx.c: 85227
59 3w-xxxx.h: 16846
71 4level-fixup.h: 1028
110 6xx-suspend.S: 1086
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