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/linux-6.8/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
24 - st,stm32f4-otp
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/linux-6.8/drivers/nvmem/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 Support for NVMEM(Non Volatile Memory) devices like EEPROM, EFUSES...
38 calibration data required for the PCIe or the USB-C PHY.
41 be called nvmem-apple-efuses.
44 tristate "Broadcom On-Chip OTP Controller support"
49 Say y here to enable read/write access to the Broadcom OTP
53 will be called nvmem-bcm-ocotp.
73 will be called nvmem-imx-iim.
76 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
80 This is a driver for the On-Chip OTP Controller (OCOTP) available on
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Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
18 #include "stm32-bsec-optee-ta.h"
20 /* BSEC secure service access from non-secure */
51 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
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/linux-6.8/sound/soc/codecs/
Dcs35l56-shared.c1 // SPDX-License-Identifier: GPL-2.0-only
17 * Firmware can change these to non-defaults to satisfy SDCA.
25 /* These are not reset by a soft-reset, so patch to defaults. */
33 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, in cs35l56_set_patch()
227 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); in cs35l56_force_sync_asp1_registers_from_cache()
232 /* Write the values cache-bypassed so that they will be written to silicon */ in cs35l56_force_sync_asp1_registers_from_cache()
233 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, in cs35l56_force_sync_asp1_registers_from_cache()
241 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); in cs35l56_force_sync_asp1_registers_from_cache()
252 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); in cs35l56_mbox_send()
253 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, in cs35l56_mbox_send()
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/linux-6.8/drivers/net/wireless/ath/wil6210/
Dwmi.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
24 " 0 - use default; < 0 - don't auto-establish");
29 " 60G device led enablement. Set the led ID (0-2) to enable");
35 * DOC: WMI event receiving - theory of operations
42 * event list @wil->pending_wmi_ev. Then, work queue @wil->wmi_wq wakes up
47 * if WMI event handling involves another WMI command flow, this 2-nd flow
52 * DOC: Addressing - theory of operations
57 * - MAC CPU (ucode)
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/linux-6.8/drivers/net/ethernet/sfc/siena/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux-6.8/drivers/net/ethernet/sfc/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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