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/qemu/hw/misc/
H A Dbcm2835_cprman.c16 * channels. Those channel are then connected to the clock muxes. Each mux has
18 * debug" clocks). A mux is configured to select a given source through its
19 * control register. Each mux has one output clock that also goes out of the
21 * (so a given mux is dedicated to a peripheral).
23 * At each level (PLL, channel and mux), the clock can be altered through
30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
31 * | |->[PLL channel] muxes takes [mux]
32 * | \->[PLL channel] inputs from [mux]
33 * | some channels [mux]
34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
[all …]
H A Dstm32l4x5_rcc.c41 * Function to simply acknowledge and propagate changes in a clock mux
46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source) in clock_mux_update() argument
49 Clock *current_source = mux->srcs[mux->src]; in clock_mux_update()
56 * This means that the multiplier of the mux becomes the divider of in clock_mux_update()
57 * the clock and the divider of the mux becomes the multiplier of the in clock_mux_update()
60 if (!bypass_source && mux->enabled && mux->divider) { in clock_mux_update()
61 freq_multiplier = mux->divider; in clock_mux_update()
64 clk_changed |= clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier); in clock_mux_update()
65 clk_changed |= clock_set(mux->out, clock_get(current_source)); in clock_mux_update()
67 clock_propagate(mux->out); in clock_mux_update()
[all …]
H A Dtrace-events190 stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled"
191 stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled"
192 …uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor changed: …
193 stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source …
194 …t32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d update: s…
/qemu/hw/i2c/
H A Di2c_mux_pca954x.c36 * @control: The value written to the mux control.
71 Pca954xState *mux = PCA954X(candidate); in OBJECT_DECLARE_TYPE() local
72 Pca954xClass *mc = PCA954X_GET_CLASS(mux); in OBJECT_DECLARE_TYPE()
75 /* They are talking to the mux itself (or all devices enabled). */ in OBJECT_DECLARE_TYPE()
86 if (!mux->enabled[i]) { in OBJECT_DECLARE_TYPE()
90 if (i2c_scan_bus(mux->bus[i], address, broadcast, in OBJECT_DECLARE_TYPE()
166 I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel) in pca954x_i2c_get_bus() argument
168 Pca954xClass *pc = PCA954X_GET_CLASS(mux); in pca954x_i2c_get_bus()
169 Pca954xState *pca954x = PCA954X(mux); in pca954x_i2c_get_bus()
229 dc->desc = "Pca954x i2c-mux"; in pca954x_class_init()
H A Dtrace-events55 # i2c-mux-pca954x.c
/qemu/chardev/
H A Dchar-mux.c35 /* MUX driver for serial I/O splitting */
304 /* Fix up the real driver with mux routines */ in mux_chr_update_read_handlers()
369 ChardevMux *mux = backend->u.mux.data; in qemu_chr_open_mux() local
373 drv = qemu_chr_find(mux->chardev); in qemu_chr_open_mux()
375 error_setg(errp, "mux: base chardev %s not found", mux->chardev); in qemu_chr_open_mux()
391 ChardevMux *mux; in qemu_chr_parse_mux() local
394 error_setg(errp, "chardev: mux: no chardev given"); in qemu_chr_parse_mux()
398 mux = backend->u.mux.data = g_new0(ChardevMux, 1); in qemu_chr_parse_mux()
399 qemu_chr_parse_common(opts, qapi_ChardevMux_base(mux)); in qemu_chr_parse_mux()
400 mux->chardev = g_strdup(chardev); in qemu_chr_parse_mux()
[all …]
H A Dchar.c374 qemu_opt_set(opts, "mux", "on", &error_abort); in qemu_chr_parse_compat()
671 if (qemu_opt_get_bool(opts, "mux", 0)) { in do_qemu_chr_new_from_opts()
684 Chardev *mux; in do_qemu_chr_new_from_opts() local
688 backend->u.mux.data = g_new0(ChardevMux, 1); in do_qemu_chr_new_from_opts()
689 backend->u.mux.data->chardev = g_strdup(bid); in do_qemu_chr_new_from_opts()
690 mux = qemu_chardev_new(id, TYPE_CHARDEV_MUX, backend, context, errp); in do_qemu_chr_new_from_opts()
691 if (mux == NULL) { in do_qemu_chr_new_from_opts()
696 chr = mux; in do_qemu_chr_new_from_opts()
704 /* RR should be set on the base device, not the mux */ in do_qemu_chr_new_from_opts()
749 if (qemu_opt_get_bool(opts, "mux", 0)) { in qemu_chr_new_from_name()
[all …]
H A Dmeson.build5 'char-mux.c',
/qemu/include/hw/i2c/
H A Di2c_mux_pca954x.h11 * mux.
12 * @mux: an i2c mux device.
17 I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel);
/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h17 #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
18 #define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
415 /* Clock mux init info */
426 * Each clock mux can have up to 10 sources. Sources 0 to 3 are always the
427 * same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are not
492 * The DSI0 channels. This one got an intermediate mux between the PLL channels
740 CprmanClockMuxState *mux, in set_clock_mux_init_info() argument
743 mux->id = id; in set_clock_mux_init_info()
744 mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset]; in set_clock_mux_init_info()
745 mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1]; in set_clock_mux_init_info()
[all …]
H A Dstm32l4x5_rcc.h27 /* In the Stm32l4x5 clock tree, mux have at most 7 sources */
38 /* NB: Prescaler are assimilated to mux with one source and one output */
72 * Mux that have only one input and one output assigned to as peripheral.
H A Dstm32l4x5_rcc_internals.h24 #define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
410 /* Clock mux init info */
495 .name = "lcd-and-rtc-common-mux",
1028 static inline void set_clock_mux_init_info(RccClockMuxState *mux, in set_clock_mux_init_info() argument
1031 mux->id = id; in set_clock_mux_init_info()
1032 mux->multiplier = CLOCK_MUX_INIT_INFO[id].multiplier; in set_clock_mux_init_info()
1033 mux->divider = CLOCK_MUX_INIT_INFO[id].divider; in set_clock_mux_init_info()
1034 mux->enabled = CLOCK_MUX_INIT_INFO[id].enabled; in set_clock_mux_init_info()
1039 mux->src = 0; in set_clock_mux_init_info()
H A Dxlnx-versal-pmc-iou-slcr.h48 * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
50 * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
H A Dnpcm_clk.h45 /* SEL/MUX in CLK module. */
/qemu/target/hexagon/imported/
H A Dcompare.idef211 /* Mux instructions */
213 Q6INSN(C2_mux,"Rd32=mux(Pu4,Rs32,Rt32)",ATTRIBS(),
214 "Scalar MUX",
270 Q6INSN(C2_muxii,"Rd32=mux(Pu4,#s8,#S8)",ATTRIBS(A_ARCHV2),
271 "Scalar MUX immediates",
276 Q6INSN(C2_muxir,"Rd32=mux(Pu4,Rs32,#s8)",ATTRIBS(A_ARCHV2),
277 "Scalar MUX register immediate",
281 Q6INSN(C2_muxri,"Rd32=mux(Pu4,#s8,Rs32)",ATTRIBS(A_ARCHV2),
282 "Scalar MUX register immediate",
288 "Vector MUX",
/qemu/tests/unit/
H A Dtest-char.c190 /* Create mux and chardev to be immediately removed */ in char_mux_test()
191 opts = qemu_opts_create(qemu_find_opts("chardev"), "mux-label", in char_mux_test()
195 qemu_opt_set(opts, "mux", "on", &error_abort); in char_mux_test()
200 /* Remove just created mux and chardev */ in char_mux_test()
201 qmp_chardev_remove("mux-label", &error_abort); in char_mux_test()
202 qmp_chardev_remove("mux-label-base", &error_abort); in char_mux_test()
204 opts = qemu_opts_create(qemu_find_opts("chardev"), "mux-label", in char_mux_test()
208 qemu_opt_set(opts, "mux", "on", &error_abort); in char_mux_test()
232 base = qemu_chr_find("mux-label-base"); in char_mux_test()
348 data = qmp_ringbuf_read("mux-label-base", 128, false, 0, &error_abort); in char_mux_test()
[all …]
/qemu/docs/system/
H A Dmux-chardev.rst6 .. include:: mux-chardev.rst.inc
H A Dindex.rst19 mux-chardev
H A Dqemu-manpage.rst43 .. include:: mux-chardev.rst.inc
/qemu/include/chardev/
H A Dchar.h23 CHR_EVENT_MUX_IN, /* mux-focus was set to this terminal */
24 CHR_EVENT_MUX_OUT, /* mux-focus will move on */
234 #define TYPE_CHARDEV_MUX "chardev-mux"
/qemu/qapi/
H A Dchar.json325 # Configuration info for mux chardevs.
493 # @mux: (since 1.5)
538 'mux',
607 # @data: Configuration info for mux chardevs
731 'mux': 'ChardevMuxWrapper',
/qemu/include/hw/ssi/
H A Dxlnx-versal-ospi.h45 * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
H A Dssi.h8 * chip select. This is implemented in qemu by having an explicit mux device.
/qemu/tests/tcg/arm/
H A DMakefile.softmmu-target52 QEMU_SEMIHOST=-serial none -chardev stdio,mux=on,id=stdio0 -semihosting-config enable=on,chardev=st…
/qemu/hw/arm/
H A Dxlnx-versal.c576 "ospi-mux-sel", 0); in versal_create_ospi()
577 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, in versal_create_ospi()
898 "qspi-ospi-mux-sel-dummy", 1); in versal_unimp()
910 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); in versal_unimp()
912 "qspi-ospi-mux-sel", 0, in versal_unimp()

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