Searched full:msdc (Results 1 – 8 of 8) sorted by relevance
7 title: MTK MSDC Storage Host Controller58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended65 - const: msdc256 - description: msdc subsys clock gate300 - description: msdc subsys clock gate347 interrupt-names = "msdc", "sdio_wakeup";
847 tristate "Clock driver for MediaTek MT8192 msdc"851 This driver supports MediaTek MT8192 msdc and msdc_top clocks.912 tristate "Clock driver for MediaTek MT8195 msdc"917 msdc and msdc_top clocks.
61 .name = "clk-mt8192-msdc",
130 obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
454 struct clk *src_clk; /* msdc source clock */455 struct clk *h_clk; /* msdc h_clk */457 struct clk *src_clk_cg; /* msdc source clock control gate */458 struct clk *sys_clk_cg; /* msdc subsys clock control gate */459 struct clk *crypto_clk; /* msdc crypto clock control gate */2257 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune2514 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL in msdc_cqe_cit_cal()3119 .name = "mtk-msdc",
412 /* MSDC */
812 /* MSDC */1353 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
401 * or msdc->cap_dirty_lock. List presence can also be checked while