Searched full:modelled (Results 1 – 25 of 69) sorted by relevance
123
75 on two outputs don't match. A display controller is modelled as a CRTC in KMS94 content. In KMS, each window is modelled as a plane. Each display controller105 Outputs are modelled as a composite encoder/connector pair.
192 * which should be modelled. And the data flow graph also should be modelled
31 Any connector to the data bus of this controller should be modelled using
23 modelled as a regulator.
14 be modelled as separate devices. A USB camera with a microphone will be
10 hardware devices and Linux Kernel interfaces are modelled as graph
6 * Modelled after arch/powerpc/kernel/irq.c.
16 SPMI controllers are modelled in device tree using a generic set of
44 extended RTT time to be modelled. The delay can be configured using
8 driver is loosely modelled after the generic SCSI driver, sg,
57 modelled after that in atyfb and matroxfb.
56 Any connector to the data bus of this controller should be modelled using
51 Each possible link in the ISP is modelled by a link in the Media controller
85 /* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
75 any connector to the data bus of this controller should be modelled
168 Any connector to the data bus of this controller should be modelled
6 /* Modelled after nf_nat_ipv[46]_fn().
91 The detailed behaviour for f(run) could be modelled on-line. However,
10 The Qualcomm RPM regulator is modelled as a subdevice of the RPM.
22 * Roughly modelled after the OMAP1 MPU timer code.
47 * environment. Only if the host environment is modelled as on the target
21 * Roughly modelled after the OMAP1 MPU timer code.
95 * It seems that the interrupt pipe is closely modelled after the
92 /* Generic NuBus interface functions, modelled after the PCI interface */
34 * in the user manual. So it's not modelled and forced to 0.99 * in the user manual. So it's not modelled and forced to 0.230 * The CPUX gate is not modelled - it is in a separate register (0x504)861 * The RISC-V gate is not modelled - it is in a separate register (0xd04)902 /* This clock has a second divider that is not modelled and forced to 0. */