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/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
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/linux-5.10/arch/arm/boot/dts/
Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
Dimx6qp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 ocram2: sram@940000 {
10 compatible = "mmio-sram";
15 ocram3: sram@960000 {
16 compatible = "mmio-sram";
23 compatible = "fsl,imx6qp-pre";
27 clock-names = "axi";
32 compatible = "fsl,imx6qp-pre";
36 clock-names = "axi";
41 compatible = "fsl,imx6qp-pre";
[all …]
Dat91sam9xe.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
6 * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
15 sram0: sram@2ff000 {
19 sram1: sram@300000 {
20 compatible = "mmio-sram";
22 #address-cells = <1>;
23 #size-cells = <1>;
Dat91sam9g20.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 sram0: sram@2ff000 {
22 sram1: sram@2fc000 {
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
33 compatible = "atmel,at91sam9g20-i2c";
37 compatible = "atmel,at91sam9rl-ssc";
[all …]
Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
[all …]
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
[all …]
Drda8810pl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a5";
28 sram@100000 {
29 compatible = "mmio-sram";
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Dkeystone-k2l.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
27 compatible = "arm,cortex-a15";
42 /include/ "keystone-k2l-clocks.dtsi"
45 compatible = "ti,da830-uart", "ns16550a";
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Darm,scmi.txt2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
41 Each protocol supported shall have a sub-node with corresponding compatible
[all …]
Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
[all …]
/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dmailbox.txt9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
35 mbox-names = "pwr-ctrl", "rpc";
41 sram: sram@50000000 {
42 compatible = "mmio-sram";
45 #address-cells = <1>;
46 #size-cells = <1>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dmarvell-neta-bm.txt5 - compatible: should be "marvell,armada-380-neta-bm".
6 - reg: address and length of the register set for the device.
7 - clocks: a pointer to the reference clock for this device.
8 - internal-mem: a phandle to BM internal SRAM definition.
12 - pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
17 - pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
23 refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
27 - main node:
30 compatible = "marvell,armada-380-neta-bm";
33 internal-mem = <&bm_bppi>;
[all …]
/linux-5.10/arch/arm/mach-socfpga/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-socfpga/pm.c
5 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
7 * with code from pm-imx6.c
8 * Copyright 2011-2014 Freescale Semiconductor, Inc.
35 np = of_find_compatible_node(NULL, NULL, "mmio-sram"); in socfpga_setup_ocram_self_refresh()
37 pr_err("%s: Unable to find mmio-sram in dtb\n", __func__); in socfpga_setup_ocram_self_refresh()
38 return -ENODEV; in socfpga_setup_ocram_self_refresh()
44 ret = -ENODEV; in socfpga_setup_ocram_self_refresh()
48 ocram_pool = gen_pool_get(&pdev->dev, NULL); in socfpga_setup_ocram_self_refresh()
[all …]
/linux-5.10/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.txt11 - compatible
14 - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
18 - #clock-cells : Should be 1.
19 - #power-domain-cells : Should be 1.
20 - #reset-cells : Should be 1.
26 - .../mailbox/mailbox.txt
27 - .../mailbox/nvidia,tegra186-hsp.txt
33 - .../clock/clock-bindings.txt
[all …]
/linux-5.10/drivers/misc/
Dsram.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Generic on-chip SRAM allocation driver
19 #include <soc/at91/atmel-secumod.h>
21 #include "sram.h"
33 mutex_lock(&part->lock); in sram_read()
34 memcpy_fromio(buf, part->base + pos, count); in sram_read()
35 mutex_unlock(&part->lock); in sram_read()
48 mutex_lock(&part->lock); in sram_write()
49 memcpy_toio(part->base + pos, buf, count); in sram_write()
50 mutex_unlock(&part->lock); in sram_write()
[all …]
/linux-5.10/drivers/soc/qcom/
Docmem.c1 // SPDX-License-Identifier: GPL-2.0-only
56 void __iomem *mmio; member
106 writel(data, ocmem->mmio + reg); in ocmem_write()
111 return readl(ocmem->mmio + reg); in ocmem_read()
120 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
121 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
123 if (region->mode == THIN_MODE) in update_ocmem()
127 dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", in update_ocmem()
132 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
133 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
[all …]
/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/linux-5.10/arch/arm/mach-rockchip/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
161 * after power-on. Therefore make sure, this sram region is reserved and
[all …]

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