Home
last modified time | relevance | path

Searched +full:memory +full:- +full:region (Results 1 – 25 of 391) sorted by relevance

12345678910>>...16

/qemu/docs/devel/
H A Dmemory.rst2 The memory API
5 The memory API models the memory and I/O buses and controllers of a QEMU
8 - ordinary RAM
9 - memory-mapped I/O (MMIO)
10 - memory controllers that can dynamically reroute physical memory regions
13 The memory model provides support for
15 - tracking RAM changes by the guest
16 - setting up coalesced memory for kvm
17 - setting up ioeventfd regions for kvm
19 Memory is modelled as an acyclic graph of MemoryRegion objects. Sinks
[all …]
/qemu/include/system/
H A Dmemory.h2 * Physical memory management API
10 * the COPYING file in the top-level directory.
17 #include "exec/cpu-common.h"
34 #define MAX_PHYS_ADDR (((hwaddr)1 << MAX_PHYS_ADDR_SPACE_BITS) - 1)
36 #define TYPE_MEMORY_REGION "memory-region"
40 #define TYPE_IOMMU_MEMORY_REGION "iommu-memory-region"
45 #define TYPE_RAM_DISCARD_MANAGER "ram-discard-manager"
89 * @mr: the region, or %NULL if empty
90 * @fv: the flat view of the address space the region is mapped in
94 * relative to the region's address space
[all …]
/qemu/include/hw/mem/
H A Dmemory-device.h2 * Memory Device Interface
10 * See the COPYING file in the top-level directory.
16 #include "hw/qdev-core.h"
17 #include "qapi/qapi-types-machine.h"
20 #define TYPE_MEMORY_DEVICE "memory-device"
33 * All memory devices need to implement TYPE_MEMORY_DEVICE as an interface.
35 * A memory device is a device that owns a memory region which is
37 * address in guest physical memory can either be specified explicitly
40 * Some memory device might not own a memory region in certain device
42 * empty memory devices are mostly ignored by the memory device code.
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_mem.h1 /* SPDX-License-Identifier: BSD-3-Clause */
41 #include "standard-headers/linux/types.h"
42 #include "standard-headers/linux/virtio_types.h"
43 #include "standard-headers/linux/virtio_ids.h"
44 #include "standard-headers/linux/virtio_config.h"
47 * Each virtio-mem device manages a dedicated region in physical address
49 * for a single NUMA node are possible. A virtio-mem device is like a
50 * "resizable DIMM" consisting of small memory blocks that can be plugged
51 * or unplugged. The device driver is responsible for (un)plugging memory
54 * Virtio-mem devices can only operate on their assigned memory region in
[all …]
/qemu/include/hw/virtio/
H A Dvirtio-mem.h10 * See the COPYING file in the top-level directory.
16 #include "standard-headers/linux/virtio_mem.h"
19 #include "qapi/qapi-types-misc.h"
23 #define TYPE_VIRTIO_MEM "virtio-mem"
28 #define TYPE_VIRTIO_MEM_SYSTEM_RESET "virtio-mem-system-reset"
35 #define VIRTIO_MEM_REQUESTED_SIZE_PROP "requested-size"
36 #define VIRTIO_MEM_BLOCK_SIZE_PROP "block-size"
38 #define VIRTIO_MEM_UNPLUGGED_INACCESSIBLE_PROP "unplugged-inaccessible"
39 #define VIRTIO_MEM_EARLY_MIGRATION_PROP "x-early-migration"
41 #define VIRTIO_MEM_DYNAMIC_MEMSLOTS_PROP "dynamic-memslots"
[all …]
/qemu/linux-headers/linux/
H A Dvduse.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
23 * struct vduse_dev_config - basic configuration of a VDUSE device
61 * struct vduse_iotlb_entry - entry of IOTLB to describe one IOVA region [start, last]
63 * @start: start of the IOVA region
64 * @last: last of the IOVA region
65 * @perm: access permission of the IOVA region
67 * Structure used by VDUSE_IOTLB_GET_FD ioctl to find an overlapped IOVA region.
80 * Find the first IOVA region that overlaps with the range [start, last]
81 * and return the corresponding file descriptor. Return -EINVAL means the
82 * IOVA region doesn't exist. Caller should set start and last fields.
[all …]
/qemu/include/crypto/
H A Dhash.h25 #include "qapi/qapi-types-crypto.h"
70 * @iov: the array of memory regions to hash
74 * @errp: pointer to a NULL-initialized error object
76 * Computes the hash across all the memory regions
79 * If @result_len is set to a non-zero value by the caller, then
87 * The memory referenced in @result must be released with a call
90 * Returns: 0 on success, -1 on error
102 * @buf: the memory region to hash
106 * @errp: pointer to a NULL-initialized error object
108 * Computes the hash across all the memory region
[all …]
H A Dhmac.h8 * top-level directory.
15 #include "qapi/qapi-types-crypto.h"
41 * @errp: pointer to a NULL-initialized error object
63 * Release the memory associated with @hmac that was
73 * @iov: the array of memory regions to hmac
77 * @errp: pointer to a NULL-initialized error object
79 * Computes the hmac across all the memory regions
82 * If @result_len is set to a non-zero value by the caller, then
90 * The memory referenced in @result must be released with a call
94 * 0 on success, -1 on error
[all …]
/qemu/hw/remote/
H A Dmemory.c2 * Memory manager for remote device
7 * See the COPYING file in the top-level directory.
13 #include "hw/remote/memory.h"
23 QTAILQ_FOREACH_SAFE(subregion, &sysmem->subregions, subregions_link, next) { in remote_sysmem_reset()
24 if (subregion->ram) { in remote_sysmem_reset()
34 SyncSysmemMsg *sysmem_info = &msg->data.sync_sysmem; in remote_sysmem_reconfig()
37 int region; in remote_sysmem_reconfig() local
43 for (region = 0; region < msg->num_fds; region++, suffix++) { in remote_sysmem_reconfig()
44 g_autofree char *name = g_strdup_printf("remote-mem-%u", suffix); in remote_sysmem_reconfig()
47 name, sysmem_info->sizes[region], in remote_sysmem_reconfig()
[all …]
H A Dproxy.c5 * See the COPYING file in the top-level directory.
14 #include "io/channel-util.h"
15 #include "hw/qdev-properties.h"
19 #include "hw/remote/mpqemu-link.h"
20 #include "qemu/error-report.h"
21 #include "hw/remote/proxy-memory-listener.h"
33 int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; in proxy_intx_update()
35 if (dev->virq != -1) { in proxy_intx_update()
36 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); in proxy_intx_update()
37 dev->virq = -1; in proxy_intx_update()
[all …]
/qemu/qapi/
H A Dpci.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
6 # SPDX-License-Identifier: GPL-2.0-or-later
15 # A PCI device memory region
28 # Information about a PCI device I/O region.
30 # @bar: the index of the Base Address Register for this region
33 # - 'io' if the region is a PIO region
34 # - 'memory' if the region is a MMIO region
36 # @address: memory address
38 # @size: memory size
[all …]
H A Dcxl.json1 # -*- Mode: Python -*-
32 # @cxl-inject-general-media-event:
42 # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
46 # lower bits include some flags. See CXL r3.0 Table 8-43 General
49 # @descriptor: Memory Event Descriptor with additional memory event
50 # information. See CXL r3.0 Table 8-43 General Media Event
51 # Record, Memory Event Descriptor for bit definitions.
53 # @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
54 # General Media Event Record, Memory Event Type for possible
57 # @transaction-type: Type of first transaction that caused the event
[all …]
/qemu/docs/specs/
H A Dstandard-vga.rst9 ``-vga std``
10 picks isa for -M isapc, otherwise pci
11 ``-device VGA``
13 ``-device isa-vga``
15 ``-device secondary-vga``
16 legacy-free pci variant
20 --------
27 PCI Region 0
28 Framebuffer memory, 16 MB in size (by default).
31 PCI Region 1
[all …]
/qemu/docs/interop/
H A Dvhost-user.rst4 Vhost-user Protocol
11 version 2 or later. See the COPYING file in the top-level
26 The protocol defines 2 sides of the communication, *front-end* and
27 *back-end*. The *front-end* is the application that shares its virtqueues, in
28 our case QEMU. The *back-end* is the consumer of the virtqueues.
30 In the current implementation QEMU is the *front-end*, and the *back-end*
33 or a block device back-end processing read & write to a virtual
34 disk. In order to facilitate interoperability between various back-end
38 The *front-end* and *back-end* can be either a client (i.e. connecting) or
42 --------------------------------------
[all …]
/qemu/hw/mem/
H A Dmemory-device.c2 * Memory Device Interface
9 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
14 #include "hw/mem/memory-device.h"
20 #include "system/address-spaces.h"
29 /* dropping const here is fine as we don't touch the memory region */ in memory_device_is_empty()
30 mr = mdc->get_memory_region((MemoryDeviceState *)md, &local_err); in memory_device_is_empty()
45 const uint64_t addr_a = mdc_a->get_addr(md_a); in memory_device_addr_sort()
46 const uint64_t addr_b = mdc_b->get_addr(md_b); in memory_device_addr_sort()
51 return -1; in memory_device_addr_sort()
[all …]
/qemu/docs/
H A Digd-assign.txt1 Intel Graphics Device (IGD) assignment with vfio-pci
4 Using vfio-pci, we can passthrough Intel Graphics Device (IGD) to guest, either
8 memory regions other than BARs. Special handling is required to make them work
13 * Data Stolen Memory (DSM) region used as VRAM at early stage (BIOS/UEFI)
16 (*-Required by)
19 |---------------------------------------------|-------|---------|-------|---------|
30 For #1, the "x-igd-opregion=on" option exposes a copy of host IGD OpRegion to
33 For #2, "x-igd-lpc=on" option copies the IDs of host LPC bridge and host bridge
42 For #5, "x-vga=on" enables guest access to standard VGA IO/MMIO ranges.
57 x-igd-opregion=on,x-igd-lpc=on,x-vga=on
[all …]
/qemu/include/hw/misc/
H A Dtz-mpc.h2 * ARM AHB5 TrustZone Memory Protection Controller emulation
12 /* This is a model of the TrustZone memory protection controller (MPC).
13 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
15 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
17 * The MPC sits in front of memory and allows secure software to
25 * + sysbus MMIO region 0: MemoryRegion for the MPC's config registers
26 * + sysbus MMIO region 1: MemoryRegion for the upstream end of the MPC
27 * + Property "downstream": MemoryRegion defining the downstream memory
28 * + Named GPIO output "irq": set for a transaction-failed interrupt
37 #define TYPE_TZ_MPC "tz-mpc"
[all …]
H A Divshmem-flat.h2 * Inter-VM Shared Memory Flat Device
4 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "chardev/char-fe.h"
17 #include "system/memory.h"
27 * + QOM property "shmem-size" sets the size of the RAM region shared between
29 * + sysbus MMIO region 0: device I/O mapped registers
30 * + sysbus MMIO region 1: shared memory with ivshmem server
34 #define TYPE_IVSHMEM_FLAT "ivshmem-flat"
39 /* Ivshmem registers. See ./docs/specs/ivshmem-spec.txt for details. */
80 /* Shared memory */
/qemu/hw/pci/
H A Dpci-hmp-cmds.c10 * the COPYING file in the top-level directory.
12 * Contributions after 2012-01-13 are licensed under the terms of the
21 #include "pci-internal.h"
24 #include "qapi/qapi-commands-pci.h"
29 PciMemoryRegionList *region; in hmp_info_pci_device() local
31 monitor_printf(mon, " Bus %2" PRId64 ", ", dev->bus); in hmp_info_pci_device()
33 dev->slot, dev->function); in hmp_info_pci_device()
36 if (dev->class_info->desc) { in hmp_info_pci_device()
37 monitor_puts(mon, dev->class_info->desc); in hmp_info_pci_device()
39 monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class); in hmp_info_pci_device()
[all …]
/qemu/include/hw/ssi/
H A Dnpcm7xx_fiu.h31 * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
32 * @direct_access: Memory region for direct flash access.
41 * NPCM7xxFIUState - Device state for one Flash Interface Unit.
43 * @mmio: Memory region for register access.
45 * @active_cs: Currently active chip select, or -1 if no chip is selected.
47 * @flash: Array of @cs_count per-flash-chip state objects.
52 * selects. Each chip select has a dedicated memory region which may be used to
53 * read and write the flash connected to that chip select as if it were memory.
71 #define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
/qemu/tests/tcg/multiarch/system/
H A Dvalidate-memory-counts.py3 # validate-memory-counts.py: check we instrumented memory properly
6 # - the mem plugin output
7 # - the memory binary output
11 # SPDX-License-Identifier: GPL-2.0-or-later
49 Region Base, Reads, Writes, Seen all
66 if line.startswith("Region Base"):
84 def main() -> None:
89 parser = ArgumentParser(description="Validate memory instrumentation")
93 help="The output from memory plugin")
94 parser.add_argument('--bss-cleared',
[all …]
/qemu/hw/tpm/
H A Dtpm_ppi.h10 * See the COPYING file in the top-level directory.
15 #include "system/memory.h"
25 * @m: the address-space / MemoryRegion to use
26 * @addr: the address of the PPI region
29 * Register the TPM PPI memory region at @addr on the given address
39 * Function to call on machine reset. It will check if the "Memory
40 * overwrite" variable is set, and perform a memory clear on volatile
41 * memory if requested.
/qemu/hw/display/
H A Dqxl.h8 #include "ui/qemu-spice.h"
9 #include "ui/spice-display.h"
113 /* user-friendly properties (in megabytes) */
128 #define TYPE_PCI_QXL "pci-qxl"
138 if (_qxl->debug >= _level) { \
139 fprintf(stderr, "qxl-%d: ", _qxl->id); \
148 * qxl_phys2virt: Get a pointer within a PCI VRAM memory region.
152 * @group_id: memory slot group
156 * active slot @group_id of the PCI VGA RAM memory region associated with
158 * of the memory region, returns NULL.
[all …]
/qemu/include/hw/vfio/
H A Dvfio-region.h2 * VFIO region
6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "system/memory.h"
25 off_t fd_offset; /* offset of region within device fd */
28 uint32_t flags; /* VFIO region flags (rd/wr/mmap) */
31 uint8_t nr; /* cache the region number for debug */
40 int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region,
42 int vfio_region_mmap(VFIORegion *region);
43 void vfio_region_mmaps_set_enabled(VFIORegion *region, bool enabled);
44 void vfio_region_unmap(VFIORegion *region);
[all …]
/qemu/include/hw/
H A Dregister.h8 * the COPYING file in the top-level directory.
14 #include "hw/qdev-core.h"
15 #include "system/memory.h"
28 * @ro: whether or not the bit is read-only
90 #define TYPE_REGISTER "qemu-register"
102 * @mem: optional Memory region for the register
154 * Memory API MMIO write handler that will write to a Register API register.
165 * Memory API MMIO read handler that will read from a Register API register.
184 * @ops: Memory region ops to access registers.
186 * @memory_size: Size of the memory region
[all …]

12345678910>>...16