Searched full:maintenance (Results 1 – 25 of 389) sorted by relevance
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
| D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …are prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 …o counted. Also note that this event does not count walks triggered by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
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| D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| D | l2_cache.json | 36 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
40 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
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| D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| D | l2_cache.json | 40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
32 …able walk are counted. This event does not count table walks caused by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
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| D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
40 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
44 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
48 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| D | l2_cache.json | 40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …are prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 …o counted. Also note that this event does not count walks triggered by TLB maintenance operations."
44 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 …hether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
52 …ns from both data and instruction fetch except for those caused by TLB maintenance operations or h…
56 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
60 …ations from both data and instruction fetch except for those caused by TLB maintenance operations."
[all …]
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| D | l1d_cache.json | 12 …victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The…
44 …cache line allocation. This event does not count evictions caused by cache maintenance operations."
48 …t of a coherency operation made by another CPU. Event count includes cache maintenance operations."
52 …dation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO…
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| D | l2_cache.json | 40 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
44 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| /linux-6.15/Documentation/edac/ |
| D | memory_repair.rst | 27 Post Package Repair is a maintenance operation which requests the memory
33 features implements maintenance operations. DRAM components support those
47 8.2.9.7.1.1 PPR Maintenance Operations, 8.2.9.7.1.2 sPPR Maintenance Operation
48 and 8.2.9.7.1.3 hPPR Maintenance Operation for more details.
77 See CXL spec 3.1 [1]_ section 8.2.9.7.1.4 Memory Sparing Maintenance
91 host of the need for a repair maintenance operation by using an event
92 record where the "maintenance needed" flag is set. The event record
96 rasdaemon) initiate a repair maintenance operation in response to the
100 region when maintenance need flag set or an uncorrected memory error or
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
| D | tlb.json | 12 …e broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 …s from both data and instruction fetch, except for those caused by TLB maintenance operations and …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …are prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
32 …o counted. Also note that this event does not count walks triggered by TLB maintenance operations."
60 …are prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
64 …o counted. Also note that this event does not count walks triggered by TLB maintenance operations."
68 …are prefetchers, and that this event does not count walks triggered by TLB maintenance operations."
72 …o counted. Also note that this event does not count walks triggered by TLB maintenance operations."
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| D | l2_cache.json | 48 …-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n…
52 …maintenance operations that operate by a virtual address, or by external coherency operations. Thi…
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| /linux-6.15/include/linux/ |
| D | power_supply.h | 387 * @charge_current_max_ua: maintenance charging current that is used to keep
390 * reach this voltage the maintenance charging current is turned off. It is
392 * @charge_voltage_max_uv: maintenance charging voltage that is usually a bit
395 * @safety_timer_minutes: maintenance charging safety timer, with an expiry
396 * time in minutes. We will only use maintenance charging in this setting
398 * maintenance charge current and voltage pair in respective array and wait
423 * To prolong the life of the battery, maintenance charging is applied after
434 * Maintenance charging uses the voltages from this table: a table of settings
436 * CC/CV charging. The maintenance charging will for safety reasons not go on
437 * indefinately: we lower the current and voltage with successive maintenance
[all …]
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| D | memregion.h | 32 * Perform cache maintenance after a memory event / operation that
46 * the cache maintenance.
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| /linux-6.15/arch/powerpc/sysdev/ |
| D | fsl_rio.c | 7 * - fixed maintenance access routines, check for aligned access
136 * @len: Length (in bytes) of the maintenance transaction
158 * @len: Length (in bytes) of the maintenance transaction
177 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
183 * @len: Length (in bytes) of the maintenance transaction
186 * Generates a MPC85xx read maintenance transaction. Returns %0 on
203 /* 16MB maintenance window possible */ in fsl_rio_config_read()
204 /* allow only aligned access to maintenance registers */ in fsl_rio_config_read()
242 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
248 * @len: Length (in bytes) of the maintenance transaction
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| /linux-6.15/Documentation/arch/riscv/ |
| D | patch-acceptance.rst | 3 arch/riscv maintenance guidelines for developers
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
50 Foundation. To avoid the maintenance complexity and potential
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| /linux-6.15/Documentation/driver-api/rapidio/ |
| D | tsi721.rst | 9 It supports maintenance read and write operations, inbound and outbound RapidIO
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
78 One BDMA channel is reserved for generation of maintenance read/write requests.
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| /linux-6.15/drivers/power/supply/ |
| D | ab8500_chargalg.c | 51 * full charging cycle in the case where maintenance charging
201 * @maintenance_chg: indicate if maintenance charge is active
220 * @maintenance_timer: maintenance charging timer
278 * the maintenance timer
281 * This function gets called when the maintenance timer
291 dev_dbg(di->dev, "Maintenance timer expired\n"); in ab8500_chargalg_maintenance_timer_expired()
422 * ab8500_chargalg_start_maintenance_timer() - Start charging maintenance timer
424 * @duration: duration of the maintenance timer in minutes
426 * The maintenance timer is used to maintain the charge in the battery once
442 * ab8500_chargalg_stop_maintenance_timer() - Stop maintenance timer
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | srio.txt | 64 memory and maintenance transactions then a single LIODN is
68 memory transactions and a unique LIODN for maintenance
72 represents the LIODN associated with maintenance transactions
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| /linux-6.15/arch/arm/include/asm/ |
| D | switch_to.h | 10 * during a TLB maintenance operation, so execute an inner-shareable dsb
11 * to ensure that the maintenance completes in case we migrate to another
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| /linux-6.15/include/uapi/misc/ |
| D | fastrpc.h | 24 * The driver is responsible for cache maintenance when passed
30 * CPU and DSP cache maintenance for the buffer. Get virtual address
35 * cache maintenance for the buffer.
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| /linux-6.15/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| D | mmu.json | 39 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
42 …: "Duration of a translation table walk requested by a CP15 operation (maintenance by MVA and VA t…
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