Searched full:ltdc (Results 1 – 25 of 33) sorted by relevance
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| /linux-6.8/Documentation/devicetree/bindings/display/ |
| D | st,stm32-ltdc.yaml | 4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
15 const: st,stm32-ltdc
40 ltdc has one video port with up to 2 endpoints:
61 ltdc: display-controller@40016800 {
62 compatible = "st,stm32-ltdc";
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| D | st,stm32-dsi.yaml | 58 DSI input port node, connected to the ltdc rgb output port.
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| /linux-6.8/drivers/gpu/drm/stm/ |
| D | drv.c | 29 #include "ltdc.h"
235 { .compatible = "st,stm32-ltdc"},
257 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
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| D | Makefile | 4 ltdc.o
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| D | ltdc.c | 42 #include "ltdc.h"
125 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
815 /* immediately commit disable of layers before switching off LTDC */ in ltdc_crtc_atomic_disable()
955 /* Convert video timings to ltdc timings */ in ltdc_crtc_mode_set_nofb()
1488 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); in ltdc_plane_atomic_update()
1494 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); in ltdc_plane_atomic_update()
1499 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); in ltdc_plane_atomic_update()
1729 /* Disable LTDC */ in ltdc_encoder_disable()
1747 /* Enable LTDC */ in ltdc_encoder_enable()
1997 DRM_ERROR("Unable to get ltdc registers\n"); in ltdc_load()
[all …]
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| /linux-6.8/Documentation/devicetree/bindings/clock/ |
| D | st,stm32mp1-rcc.yaml | 38 For example on STM32MP1, for LTDC reset:
39 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
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| /linux-6.8/arch/arm/boot/dts/st/ |
| D | stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 78 <dc {
91 ltdc_pins: ltdc-0 {
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| D | stm32f429-disco.dts | 156 <dc {
194 /* Connect panel-ilitek-9341 to ltdc */
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| D | stm32mp157c-dk2.dts | 73 <dc {
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| D | stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 94 <dc {
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| D | stm32mp157a-icore-stm32mp1-edimm2.2.dts | 94 <dc {
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| D | stm32f746.dtsi | 618 ltdc: display-controller@40016800 { label
619 compatible = "st,stm32-ltdc";
622 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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| D | stm32f429.dtsi | 670 ltdc: display-controller@40016800 { label
671 compatible = "st,stm32-ltdc";
674 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
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| D | stm32h743.dtsi | 353 ltdc: display-controller@50001000 { label
354 compatible = "st,stm32-ltdc";
357 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
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| D | stm32mp157c-osd32mp1-red.dts | 133 <dc {
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| D | stm32f746-disco.dts | 151 <dc {
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| D | stm32f469-disco.dts | 171 <dc {
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| D | stm32mp157c-lxa-mc1.dts | 157 <dc {
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| D | stm32f4-pinctrl.dtsi | 284 ltdc_pins_a: ltdc-0 {
318 ltdc_pins_b: ltdc-1 {
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| D | stm32429i-eval.dts | 240 <dc {
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| D | stm32mp15xx-dhcom-pdk2.dtsi | 217 <dc {
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| D | stm32mp15-pinctrl.dtsi | 865 ltdc_pins_a: ltdc-0 {
902 ltdc_sleep_pins_a: ltdc-sleep-0 {
936 ltdc_pins_b: ltdc-1 {
973 ltdc_sleep_pins_b: ltdc-sleep-1 {
1007 ltdc_pins_c: ltdc-2 {
1043 ltdc_sleep_pins_c: ltdc-sleep-2 {
1071 ltdc_pins_d: ltdc-3 {
1113 ltdc_sleep_pins_d: ltdc-sleep-3 {
1147 ltdc_pins_e: ltdc-4 {
1190 ltdc_sleep_pins_e: ltdc-sleep-4 {
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| D | stm32mp157c-ev1.dts | 233 <dc {
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| D | stm32mp15xx-dhcor-avenger96.dtsi | 354 <dc {
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| /linux-6.8/include/dt-bindings/clock/ |
| D | stm32mp1-clks.h | 69 #define LTDC 56 macro
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