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/linux-5.10/Documentation/devicetree/bindings/display/
Dst,stm32-ltdc.yaml4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
15 const: st,stm32-ltdc
41 ltdc has one video port with up to 2 endpoints:
64 ltdc: display-controller@40016800 {
65 compatible = "st,stm32-ltdc";
Dst,stm32-dsi.yaml64 DSI input port node, connected to the ltdc rgb output port.
/linux-5.10/Documentation/devicetree/bindings/clock/
Dst,stm32mp1-rcc.yaml38 For example on STM32MP1, for LTDC reset:
39 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
/linux-5.10/drivers/gpu/drm/stm/
Ddrv.c27 #include "ltdc.h"
224 { .compatible = "st,stm32-ltdc"},
245 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
Dltdc.c38 #include "ltdc.h"
114 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
457 /* immediately commit disable of layers before switching off LTDC */ in ltdc_crtc_atomic_disable()
551 /* Convert video timings to ltdc timings */ in ltdc_crtc_mode_set_nofb()
851 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); in ltdc_plane_atomic_update()
855 DRM_WARN("ltdc transfer error\n"); in ltdc_plane_atomic_update()
1039 /* Disable LTDC */ in ltdc_encoder_disable()
1053 /* Enable LTDC */ in ltdc_encoder_enable()
1262 DRM_ERROR("Unable to get ltdc registers\n"); in ltdc_load()
1278 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); in ltdc_load()
[all …]
DMakefile4 ltdc.o
/linux-5.10/arch/arm/boot/dts/
Dstm32f429-disco.dts158 &ltdc {
196 /* Connect panel-ilitek-9341 to ltdc */
Dstm32mp157c-dk2.dts80 &ltdc {
Dstm32h743.dtsi337 ltdc: display-controller@50001000 { label
338 compatible = "st,stm32-ltdc";
341 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
Dstm32f429.dtsi695 ltdc: display-controller@40016800 { label
696 compatible = "st,stm32-ltdc";
699 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
Dstm32mp15-pinctrl.dtsi489 ltdc_pins_a: ltdc-0 {
525 ltdc_sleep_pins_a: ltdc-sleep-0 {
558 ltdc_pins_b: ltdc-1 {
594 ltdc_sleep_pins_b: ltdc-sleep-1 {
627 ltdc_pins_c: ltdc-2 {
662 ltdc_sleep_pins_c: ltdc-sleep-2 {
689 ltdc_pins_d: ltdc-3 {
730 ltdc_sleep_pins_d: ltdc-sleep-3 {
Dstm32f469-disco.dts176 &ltdc {
Dstm32mp157c-lxa-mc1.dts156 &ltdc {
Dstm32f4-pinctrl.dtsi285 ltdc_pins_a: ltdc-0 {
319 ltdc_pins_b: ltdc-1 {
Dstm32mp15xx-dhcom-pdk2.dtsi196 &ltdc {
Dstm32429i-eval.dts241 &ltdc {
Dstm32mp157c-ev1.dts237 &ltdc {
Dstm32mp15xx-dhcor-avenger96.dtsi238 &ltdc {
Dstm32mp15xx-dkx.dtsi424 &ltdc {
Dstm32mp151.dtsi1448 ltdc: display-controller@5a001000 { label
1449 compatible = "st,stm32-ltdc";
/linux-5.10/include/dt-bindings/clock/
Dstm32mp1-clks.h69 #define LTDC 56 macro
/linux-5.10/drivers/clk/
Dclk-stm32f4.c132 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
214 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
289 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
367 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
Dclk-stm32mp1.c1846 PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
Dclk-stm32h7.c1108 KER_CLKF_NOMUX(RCC_APB3ENR, 3, "ltdc", ltdc_src, CLK_SET_RATE_PARENT),
/linux-5.10/
DMAINTAINERS5931 F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml