| /linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 6 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
12 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
18 … on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
24 …cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefe…
36 …location other than the local core's L2 due to either only demand loads or demand loads plus prefe…
42 … core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefe…
48 … local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefe…
54 …ithout dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefe…
60 …d from local core's L2 without conflict due to either only demand loads or demand loads plus prefe…
66 …cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefe…
[all …]
|
| D | other.json | 365 … and Final Pump Scope was chip pump (prediction=correct) for either demand loads or data prefetch",
371 … on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
372 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
377 … on a different Node or Group (Distant), as this chip due to either demand loads or data prefetch",
378 …t Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefe…
383 …ther chip's L4 on a different Node or Group (Distant) due to either demand loads or data prefetch",
384 … on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
389 …her chip's memory on the same Node or Group (Distant) due to either demand loads or data prefetch",
390 …ory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
395 …cessor's data cache was reloaded from local core's L2 due to either demand loads or data prefetch",
[all …]
|
| D | memory.json | 18 …ory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefe…
24 …s reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefe…
30 …cluding L4 from local remote or distant due to either only demand loads or demand loads plus prefe…
36 … L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefe…
42 …ory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefe…
|
| /linux-5.10/tools/perf/util/ |
| D | mem-events.h | 61 u32 load; /* count of all loads in trace */
62 u32 ld_excl; /* exclusive loads, rmt/lcl DRAM - snp none/miss */
63 u32 ld_shared; /* shared loads, rmt/lcl DRAM - snp hit */
64 u32 ld_uncache; /* loads to uncacheable address */
65 u32 ld_io; /* loads to io address */
66 u32 ld_miss; /* loads miss */
68 u32 ld_fbhit; /* count of loads hitting Fill Buffer */
69 u32 ld_l1hit; /* count of loads that hit L1D */
70 u32 ld_l2hit; /* count of loads that hit L2D */
71 u32 ld_llchit; /* count of loads that hit LLC */
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | memory.json | 7 "EventName": "MISALIGN_MEM_REF.LOADS",
42 "PublicDescription": "Loads with latency value being above 4.",
50 "BriefDescription": "Loads with latency value being above 4",
56 "PublicDescription": "Loads with latency value being above 8.",
64 "BriefDescription": "Loads with latency value being above 8",
70 "PublicDescription": "Loads with latency value being above 16.",
78 "BriefDescription": "Loads with latency value being above 16",
84 "PublicDescription": "Loads with latency value being above 32.",
92 "BriefDescription": "Loads with latency value being above 32",
98 "PublicDescription": "Loads with latency value being above 64.",
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | memory.json | 7 "EventName": "MISALIGN_MEM_REF.LOADS",
315 "BriefDescription": "Loads with latency value being above 4",
322 "PublicDescription": "This event counts loads with latency value being above four.",
330 "BriefDescription": "Loads with latency value being above 8",
337 "PublicDescription": "This event counts loads with latency value being above eight.",
345 "BriefDescription": "Loads with latency value being above 16",
352 "PublicDescription": "This event counts loads with latency value being above 16.",
360 "BriefDescription": "Loads with latency value being above 32",
367 "PublicDescription": "This event counts loads with latency value being above 32.",
375 "BriefDescription": "Loads with latency value being above 64",
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | memory.json | 7 "EventName": "MISALIGN_MEM_REF.LOADS",
33 "PublicDescription": "Loads with latency value being above 4.",
41 "BriefDescription": "Loads with latency value being above 4",
47 "PublicDescription": "Loads with latency value being above 8.",
55 "BriefDescription": "Loads with latency value being above 8",
61 "PublicDescription": "Loads with latency value being above 16.",
69 "BriefDescription": "Loads with latency value being above 16",
75 "PublicDescription": "Loads with latency value being above 32.",
83 "BriefDescription": "Loads with latency value being above 32",
89 "PublicDescription": "Loads with latency value being above 64.",
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | memory.json | 293 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl…
302 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
308 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl…
317 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
323 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl…
332 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
338 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl…
347 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
353 …"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to compl…
362 …"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to comple…
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | memory.json | 7 "EventName": "MISALIGN_MEM_REF.LOADS",
315 "BriefDescription": "Randomly selected loads with latency value being above 4",
322 "PublicDescription": "Counts randomly selected loads with latency value being above four.",
330 "BriefDescription": "Randomly selected loads with latency value being above 8",
337 "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
345 "BriefDescription": "Randomly selected loads with latency value being above 16",
352 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
360 "BriefDescription": "Randomly selected loads with latency value being above 32",
367 "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
375 "BriefDescription": "Randomly selected loads with latency value being above 64",
[all …]
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | memory.json | 21 "BriefDescription": "Loads with latency value being above 4 .",
34 "BriefDescription": "Loads with latency value being above 8.",
47 "BriefDescription": "Loads with latency value being above 16.",
60 "BriefDescription": "Loads with latency value being above 32.",
73 "BriefDescription": "Loads with latency value being above 64.",
86 "BriefDescription": "Loads with latency value being above 128.",
99 "BriefDescription": "Loads with latency value being above 256.",
112 "BriefDescription": "Loads with latency value being above 512.",
132 "EventName": "MISALIGN_MEM_REF.LOADS",
|
| /linux-5.10/tools/arch/powerpc/include/asm/ |
| D | barrier.h | 16 * loads and stores to non-cacheable memory (e.g. I/O devices).
18 * mb() prevents loads and stores being reordered across this point.
19 * rmb() prevents loads being reordered across this point.
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | memory.json | 6 "EventName": "MISALIGN_MEM_REF.LOADS",
48 "BriefDescription": "Loads with latency value being above 4 .",
61 "BriefDescription": "Loads with latency value being above 8.",
74 "BriefDescription": "Loads with latency value being above 16.",
87 "BriefDescription": "Loads with latency value being above 32.",
100 "BriefDescription": "Loads with latency value being above 64.",
113 "BriefDescription": "Loads with latency value being above 128.",
126 "BriefDescription": "Loads with latency value being above 256.",
139 "BriefDescription": "Loads with latency value being above 512.",
|
| /linux-5.10/arch/powerpc/include/asm/ |
| D | barrier.h | 20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
32 * doesn't order loads with respect to previous stores. Lwsync can be
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/westmereep-dp/ |
| D | other.json | 88 "BriefDescription": "Loads that partially overlap an earlier store"
96 "BriefDescription": "All loads dispatched"
104 "BriefDescription": "Loads dispatched from the MOB"
112 "BriefDescription": "Loads dispatched that bypass the MOB"
120 "BriefDescription": "Loads dispatched from stage 305"
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/westmereex/ |
| D | other.json | 88 "BriefDescription": "Loads that partially overlap an earlier store"
96 "BriefDescription": "All loads dispatched"
104 "BriefDescription": "Loads dispatched from the MOB"
112 "BriefDescription": "Loads dispatched that bypass the MOB"
120 "BriefDescription": "Loads dispatched from stage 305"
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/westmereep-sp/ |
| D | other.json | 88 "BriefDescription": "Loads that partially overlap an earlier store"
96 "BriefDescription": "All loads dispatched"
104 "BriefDescription": "Loads dispatched from the MOB"
112 "BriefDescription": "Loads dispatched that bypass the MOB"
120 "BriefDescription": "Loads dispatched from stage 305"
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/nehalemep/ |
| D | other.json | 88 "BriefDescription": "All loads dispatched"
96 "BriefDescription": "Loads dispatched from the MOB"
104 "BriefDescription": "Loads dispatched that bypass the MOB"
112 "BriefDescription": "Loads dispatched from stage 305"
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/nehalemex/ |
| D | other.json | 88 "BriefDescription": "All loads dispatched"
96 "BriefDescription": "Loads dispatched from the MOB"
104 "BriefDescription": "Loads dispatched that bypass the MOB"
112 "BriefDescription": "Loads dispatched from stage 305"
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | memory.json | 23 "BriefDescription": "Counts the number of loads dispatched to the LS unit. Unit Masks ADDed.",
49 "EventName": "ls_mab_alloc.loads",
51 "BriefDescription": "LS MAB allocates by type - loads.",
147 "BriefDescription": "Misaligned loads."
|
| /linux-5.10/tools/memory-model/Documentation/ |
| D | explanation.txt | 78 for the loads, the model will predict whether it is possible for the
79 code to run in such a way that the loads will indeed obtain the
141 shared memory locations and another CPU loads from those locations in
153 A memory model will predict what values P1 might obtain for its loads
196 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
197 it, as loads can obtain values only from earlier stores.
199 P1 loads from flag before loading from buf, since CPUs execute
222 each CPU stores to its own shared location and then loads from the
271 X: P1 loads 1 from flag executes before
272 Y: P1 loads 0 from buf executes before
[all …]
|
| /linux-5.10/arch/mips/include/asm/ |
| D | sync.h | 33 * loads or stores. By way of example, if we only care that stores older
35 * barrier & don't care about the ordering of loads then the 'wmb'
37 * allows loads to continue unaffected & potentially allows the CPU to
38 * make progress faster than if younger loads had to wait for older stores
78 * A GINV sync is a little different; it doesn't relate directly to loads or
|
| /linux-5.10/tools/perf/tests/ |
| D | parse-metric.c | 27 .metric_expr = "l1d\\-loads\\-misses / inst_retired.any",
31 .metric_expr = "l1i\\-loads\\-misses / inst_retired.any",
244 { .event = "l1d-loads-misses", .val = 300 }, in test_cache_miss_cycles()
245 { .event = "l1i-loads-misses", .val = 200 }, in test_cache_miss_cycles()
329 { .event = "l1d-loads-misses", .val = 300 }, in test_metric_group()
330 { .event = "l1i-loads-misses", .val = 200 }, in test_metric_group()
|
| /linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | memory.json | 5 …duce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable t…
6 …re. Software can avoid this problem by using same-size and same-alignment loads and stores when ac…
58 …"BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the…
105 "EventName": "ls_mab_alloc.loads",
107 "BriefDescription": "LS MAB Allocates by Type. Loads.",
233 "BriefDescription": "Misaligned loads."
|
| /linux-5.10/tools/perf/Documentation/ |
| D | perf-mem.txt | 19 right set of options to display a memory access profile. By default, loads
20 and stores are sampled. Use the -t option to limit to loads or stores.
85 Specify desired latency for loads event. (x86 only)
|
| /linux-5.10/arch/mips/include/asm/octeon/ |
| D | octeon.h | 223 * loads/stores can use XKPHYS addresses with
226 /* R/W If set (and UX set), user-level loads/stores
230 * loads/stores can use XKPHYS addresses with
233 /* R/W If set (and UX set), user-level loads/stores
266 /* R/W If set, CVMSEG is available for loads/stores in
269 /* R/W If set, CVMSEG is available for loads/stores in
272 /* R/W If set, CVMSEG is available for loads/stores in
|