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/linux/tools/testing/selftests/powerpc/ptrace/
H A Dptrace-vsx.h11 * unsigned long load[128]
13 int validate_vsx(unsigned long *vsx, unsigned long *load) in validate_vsx() argument
18 if (vsx[i] != load[2 * i + 1]) { in validate_vsx()
19 printf("vsx[%d]: %lx load[%d] %lx\n", in validate_vsx()
20 i, vsx[i], 2 * i + 1, load[2 * i + 1]); in validate_vsx()
29 * unsigned long load[128]
31 int validate_vmx(unsigned long vmx[][2], unsigned long *load) in validate_vmx() argument
37 if ((vmx[i][0] != load[64 + 2 * i]) || in validate_vmx()
38 (vmx[i][1] != load[65 + 2 * i])) { in validate_vmx()
39 printf("vmx[%d][0]: %lx load[ in validate_vmx()
70 compare_vsx_vmx(unsigned long * store,unsigned long * load) compare_vsx_vmx() argument
108 load_vsx_vmx(unsigned long * load,unsigned long * vsx,unsigned long vmx[][2]) load_vsx_vmx() argument
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/linux/arch/sparc/lib/
H A DM7memcpy.S48 * load words, shift half words, store words; branch to finish_up
50 * load words, shift 3 bytes, store words; branch to finish_up
52 * load words, shift 1 byte, store words; branch to finish_up
116 #ifndef LOAD
117 #define LOAD(type,addr,dest) type [addr], dest macro
209 EX_LD(LOAD(ldub, %o4, %o4), memcpy_retl_o2_plus_o5) ! load one byte
236 EX_LD(LOAD(ldx, %o1, %o4), memcpy_retl_o2_plus_63) ! load
239 EX_LD(LOAD(ld
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H A DU3memcpy.S40 #ifndef LOAD
41 #define LOAD(type,addr,dest) type [addr], dest macro
215 EX_LD_FP(LOAD(ldub, %o1 + 0x00, %o3), U3_retl_o2_plus_g2_plus_g1_plus_1)
227 EX_LD_FP(LOAD(ldd, %o1, %f4), U3_retl_o2_plus_g2)
228 1: EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f6), U3_retl_o2_plus_g2)
236 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U3_retl_o2_plus_g2)
244 3: LOAD(prefetch, %o1 + 0x000, #one_read)
245 LOAD(prefetch, %o1 + 0x040, #one_read)
247 LOAD(prefetch, %o1 + 0x080, #one_read)
248 LOAD(prefetc
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H A DNG4memcpy.S65 #ifndef LOAD
66 #define LOAD(type,addr,dest) type [addr], dest macro
130 1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_g1)
137 51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong)
138 LOAD(prefetch, %o1 + 0x080, #n_reads_strong)
139 LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong)
140 LOAD(prefetch, %o1 + 0x100, #n_reads_strong)
141 LOAD(prefetch, %o1 + 0x140, #n_reads_strong)
142 LOAD(prefetch, %o1 + 0x180, #n_reads_strong)
143 LOAD(prefetc
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H A Dcsum_copy.S27 #ifndef LOAD
28 #define LOAD(type,addr,dest) type [addr], dest macro
50 EX_LD(LOAD(ldub, %o0 + 0x00, %o4))
60 EX_LD(LOAD(lduh, %o0 + 0x00, %o5))
72 LOAD(prefetch, %o0 + 0x000, #n_reads)
78 LOAD(prefetch, %o0 + 0x040, #n_reads)
91 LOAD(prefetch, %o0 + 0x080, #n_reads)
94 LOAD(prefetch, %o0 + 0x0c0, #n_reads)
97 LOAD(prefetch, %o0 + 0x100, #n_reads)
105 LOAD(prefetc
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H A DNG2memcpy.S50 #ifndef LOAD
51 #define LOAD(type,addr,dest) type [addr], dest macro
141 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
143 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
144 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
146 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
147 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
148 EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
150 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
151 EX_LD_FP(LOAD(ld
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/linux/arch/alpha/include/asm/
H A Dxor.h73 xor $0,$1,$0 # 7 cycles from $1 load \n\
130 xor $0,$1,$1 # 8 cycles from $0 load \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
132 xor $6,$7,$7 # 6 cycles from $7 load \n\
133 xor $21,$22,$22 # 5 cycles from $22 load \n\
135 xor $1,$2,$2 # 9 cycles from $2 load \n\
136 xor $24,$25,$25 # 5 cycles from $25 load \n\
138 xor $4,$5,$5 # 6 cycles from $5 load \n\
141 xor $7,$20,$20 # 7 cycles from $20 load \n\
143 xor $22,$23,$23 # 7 cycles from $23 load \
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/linux/tools/power/cpupower/bench/
H A DREADME-BENCH9 - Identify average reaction time of a governor to CPU load changes
34 You can specify load (100% CPU load) and sleep (0% CPU load) times in us which
38 load=25000
41 This part of the configuration file will create 25ms load/sleep turns,
48 Will increase load and sleep time by 25ms 5 times.
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/slee
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H A Dbenchmark.c25 * to get the given load time
27 * @param load aimed load time in µs
32 unsigned int calculate_timespace(long load, struct config *config) in calculate_timespace() argument
41 printf("calibrating load of %lius, please wait...\n", load); in calculate_timespace()
50 /* approximation of the wanted load time by comparing with the in calculate_timespace()
53 rounds = (unsigned int)(load * estimated / timed); in calculate_timespace()
70 * generates a specific sleep an load time with the performance
88 load_time = config->load; in start_benchmark()
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/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dmemory.json5 "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
6 "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
11 "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
12 "PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
17 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
23 "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
29 "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
35 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
41 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
47 "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
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H A Dmarked.json35 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
41 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
47 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
53 "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
59 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
65 "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
71 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
77 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
83 "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
95 "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
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H A Dcache.json5 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
11 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
17 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
23 "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
35 "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
41 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
42 "PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
47 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
53 "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
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H A Dmetrics.json297 "BriefDescription": "Cycles stalled by LSU load finishes",
492 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hit-Store conflict",
504 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 did not experience a conflict",
510 "BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced some conflict other than Load-Hit-Store",
534 "BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pending prefetch",
546 "BriefDescription": "Percentage of L3 load hits per instruction where the L3 did not experience a conflict",
594 "BriefDescription": "Percentage of L1 demand load misse
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/linux/include/linux/
H A Dhp_sdc.h175 #define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
176 #define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
177 #define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
178 #define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
179 #define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
188 #define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
189 #define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
190 #define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
191 #define HP_SDC_CMD_READ_KLC 0x12 /* Load primar
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json27 "PublicDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
30 "BriefDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
33 "PublicDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
36 "BriefDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
39 "PublicDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded",
42 "BriefDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded"
45 "PublicDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
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/linux/arch/mips/cavium-octeon/
H A Docteon-memcpy.S46 * When an exception happens on a load, the handler must
84 #define LOAD ld macro
187 EXC( LOAD t0, UNIT(0)(src), l_exc)
188 EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
189 EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
190 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
196 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
197 EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
198 EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
199 EXC( LOAD t
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/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dmemory.json3 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
11 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
19 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
27 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffe
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/linux/tools/perf/pmu-events/arch/x86/clearwaterforest/
H A Dcache.json21 "BriefDescription": "Counts the number of load ops retired.",
25 "PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1",
39 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
45 "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
50 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
56 "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
61 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
67 "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
72 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
78 "PublicDescription": "Counts the number of tagged load uop
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi32 * Most Lumia 950/XL users use GRUB to load their kernels,
582 regulator-allow-set-load;
583 regulator-system-load = <300000>;
589 regulator-allow-set-load;
591 regulator-system-load = <325000>;
597 regulator-allow-set-load;
598 regulator-system-load = <325000>;
619 regulator-allow-set-load;
620 regulator-system-load = <4160>;
627 regulator-allow-set-load;
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/linux/arch/powerpc/lib/
H A Dxor_vmx.c28 #define LOAD(V) \ macro
61 LOAD(v1); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
82 LOAD(v1); in __xor_altivec_3()
83 LOAD(v2); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
108 LOAD(v1); in __xor_altivec_4()
109 LOAD(v2); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
111 LOAD(v in __xor_altivec_4()
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/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A Dmemory.json3 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
12 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
21 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
30 "BriefDescription": "Counts the number of cycles that the head (oldest load) o
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/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Dmemory.json3 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
11 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
19 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
27 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffe
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json45 "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
60 "BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)"
135 "BriefDescription": "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491): The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region. This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56])."
145 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load"
170 "BriefDescription": "Load tm hit in L1"
205 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
225 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load"
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/linux/tools/perf/Documentation/
H A Dperf-c2c.txt22 On Intel, the tool is based on load latency and precise store facility events
26 sample load and store operations, therefore hardware and kernel support is
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
65 - Load latency filtering is disabled by default.
208 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
209 - count of Total/Local/Remote load HITMs
211 Load Peer - Total, Local, Remote (For display with peer type)
212 - count of Total/Local/Remote load from peer cache or DRAM
218 - sum of all load accesse
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/linux/net/core/
H A Dptp_classifier.c12 * ldh [12] ; load ethertype
17 * ldb [23] ; load proto
19 * ldh [20] ; load frag offset field
21 * ldxb 4*([14]&0xf) ; load IP header len
22 * ldh [x + 16] ; load UDP dst port
24 * ldh [x + 22] ; load payload
33 * ldb [20] ; load proto
35 * ldh [56] ; load UDP dst port
37 * ldh [62] ; load payload
46 * ldh [16] ; load inne
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