Searched +full:lgm +full:- +full:pcie (Results 1 – 4 of 4) sorted by relevance
| /linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCIe RC controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
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| /linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | intel,combo-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
13 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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| /linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
24 /* PCIe Application logic Registers */
88 return readl(lpp->app_base + ofs); in pcie_app_rd()
93 writel(val, lpp->app_base + ofs); in pcie_app_wr()
99 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
104 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
109 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
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| /linux-5.10/drivers/phy/intel/ |
| D | phy-intel-lgm-combo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
120 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_pcie_refclk_cfg()
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