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/qemu/scripts/
H A Dcpu-x86-uarch-abi.py6 # compatibility levels for each CPU model.
20 levels = [ variable
113 "levels": [False, False, False, False],
128 for level in range(len(levels)):
130 want = set(levels[level])
135 models[name]["levels"][level] = match
147 for level in range(len(levels)):
148 if models[name]["levels"][level]:
164 if not models[name]["levels"][level]:
174 if not models[name]["levels"][level]:
[all …]
/qemu/util/
H A Dhbitmap.c22 * that the number of levels is in fact fixed.
25 * granularity; in all levels except the last, bit N is set iff the N-th
44 * Setting or clearing a range of m bits on all levels, the work to perform
95 * Note that all bitmaps have the same number of levels. Even a 1-bit
98 unsigned long *levels[HBITMAP_LEVELS]; member
100 /* The length of each levels[] array. */
117 cur = hbi->cur[i] & hb->levels[i][pos]; in hbitmap_iter_skip_words()
139 cur = hb->levels[i + 1][pos]; in hbitmap_iter_skip_words()
152 hbi->hb->levels[HBITMAP_LEVELS - 1][hbi->pos]; in hbitmap_iter_next()
185 hbi->cur[i] = hb->levels[i][pos] & ~((1UL << bit) - 1); in hbitmap_iter_init()
[all …]
/qemu/hw/core/
H A Dor-irq.c38 s->levels[n] = level; in or_irq_handler()
41 or_level |= s->levels[i]; in or_irq_handler()
53 s->levels[i] = false; in or_irq_reset()
76 * The subsection migrates as much of the levels[] array as is needed
98 VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
109 VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
/qemu/target/riscv/
H A Dmonitor.c148 int levels, ptidxbits, ptesize, vm, va_bits; in mem_info_svxx() local
166 levels = 2; in mem_info_svxx()
171 levels = 3; in mem_info_svxx()
176 levels = 4; in mem_info_svxx()
181 levels = 5; in mem_info_svxx()
190 va_bits = PGSHIFT + levels * ptidxbits; in mem_info_svxx()
202 walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, in mem_info_svxx()
/qemu/hw/vfio/
H A Dspapr.c37 unsigned int levels; member
283 * levels number and if this fails (for example due to the host memory in vfio_spapr_create_window()
284 * fragmentation), we increase levels. The DMA address structure is: in vfio_spapr_create_window()
291 * The aim is to split "x" to smaller possible number of levels. in vfio_spapr_create_window()
304 create.levels = bits_total / bits_per_level; in vfio_spapr_create_window()
306 ddw_levels = scontainer->levels; in vfio_spapr_create_window()
309 ++create.levels; in vfio_spapr_create_window()
312 for ( ; create.levels <= max_levels; ++create.levels) { in vfio_spapr_create_window()
319 if (create.levels > ddw_levels) { in vfio_spapr_create_window()
342 create.levels, in vfio_spapr_create_window()
[all …]
/qemu/hw/intc/
H A Dheathrow_pic.c35 return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask; in heathrow_check_irq()
98 value = pic->levels; in heathrow_read()
124 last_level = (pic->levels & irq_bit) ? 1 : 0; in heathrow_set_irq()
128 pic->levels |= irq_bit; in heathrow_set_irq()
130 pic->levels &= ~irq_bit; in heathrow_set_irq()
147 VMSTATE_UINT32(levels, HeathrowPICState),
/qemu/docs/specs/
H A Dppc-spapr-numa.rst51 the NUMA levels for the platform.
67 three NUMA levels:
77 P2 processors, we would have the following NUMA levels:
150 the distance of the previous level, and the maximum amount of levels is
156 * resources two NUMA levels apart: 40
157 * resources three NUMA levels apart: 80
158 * resources four NUMA levels apart: 160
168 for 4 distinct NUMA distance values based on the NUMA levels
171 NUMA levels, granting user flexibility
/qemu/docs/system/
H A Dcpu-models-x86.rst.inc42 ABI compatibility levels for CPU models
45 The x86_64 architecture has a number of `ABI compatibility levels`_
49 table that follows illustrates which ABI compatibility levels
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
85 Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
/qemu/include/hw/intc/
H A Darm_gic_common.h46 /* Only 32 priority levels and 32 preemption levels in the vCPU interfaces */
H A Dheathrow_pic.h38 uint32_t levels; member
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h190 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
193 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
204 /* Masks of interrupts at each range 1..n of interrupt levels: */
281 /* Interrupt numbers for levels at which only one interrupt is configured: */
290 * External interrupt vectors/levels.
/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h186 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
189 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
200 /* Masks of interrupts at each range 1..n of interrupt levels: */
264 /* Interrupt numbers for levels at which only one interrupt is configured: */
269 * External interrupt vectors/levels.
/qemu/hw/misc/macio/
H A Dgpio.c108 /* Levels regs are read-only */ in macio_gpio_write()
132 /* Levels regs */ in macio_gpio_read()
/qemu/linux-headers/asm-mips/
H A Dsgidefs.h15 * Definitions for the ISA levels
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h257 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
260 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
271 /* Masks of interrupts at each range 1..n of interrupt levels: */
328 /* Interrupt numbers for levels at which only one interrupt is configured: */
333 * External interrupt vectors/levels.
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h270 #define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
273 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
284 /* Masks of interrupts at each range 1..n of interrupt levels: */
347 /* Interrupt numbers for levels at which only one interrupt is configured: */
353 * External interrupt vectors/levels.
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h238 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
241 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
252 /* Masks of interrupts at each range 1..n of interrupt levels: */
329 /* Interrupt numbers for levels at which only one interrupt is configured: */
338 * External interrupt vectors/levels.
/qemu/linux-user/generic/
H A Dsockbits.h40 /* Security levels - as per NRL IPv6 - don't actually do anything */
/qemu/include/hw/
H A Dor-irq.h44 bool levels[MAX_OR_LINES]; member
/qemu/bsd-user/
H A Derrno_defs.h112 #define TARGET_ELOOP 62 /* Too many levels of symbolic links */
127 #define TARGET_EREMOTE 71 /* Too many levels of remote in path */
/qemu/linux-user/alpha/
H A Dsockbits.h59 /* Security levels - as per NRL IPv6 - don't actually do anything */
/qemu/include/hw/southbridge/
H A Dpiix.h39 * bitmap to track pic levels.
/qemu/linux-user/sparc/
H A Dsockbits.h107 /* Security levels - as per NRL IPv6 - don't actually do anything */
/qemu/qapi/
H A Dmachine-common.json25 # An enumeration of CPU topology levels.
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h263 #define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
266 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
277 /* Masks of interrupts at each range 1..n of interrupt levels: */
332 /* Interrupt numbers for levels at which only one interrupt is configured: */

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