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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
57 …DC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/linux/fs/nilfs2/
H A Dbtree.c26 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_alloc_path() local
32 for (; level < NILFS_BTREE_LEVEL_MAX; level++) { in nilfs_btree_alloc_path()
33 path[level].bp_bh = NULL; in nilfs_btree_alloc_path()
34 path[level].bp_sib_bh = NULL; in nilfs_btree_alloc_path()
35 path[level].bp_index = 0; in nilfs_btree_alloc_path()
36 path[level].bp_oldreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
37 path[level].bp_newreq.bpr_ptr = NILFS_BMAP_INVALID_PTR; in nilfs_btree_alloc_path()
38 path[level].bp_op = NULL; in nilfs_btree_alloc_path()
47 int level = NILFS_BTREE_LEVEL_DATA; in nilfs_btree_free_path() local
49 for (; level < NILFS_BTREE_LEVEL_MAX; level++) in nilfs_btree_free_path()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This…
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i…
56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
[all …]
/linux/lib/zstd/compress/
H A Dclevels.h28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
32 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
33 { 21, 18, 19, 3, 5, 4, ZSTD_lazy }, /* level 6 */
34 { 21, 19, 20, 4, 5, 8, ZSTD_lazy }, /* level 7 */
35 { 21, 19, 20, 4, 5, 16, ZSTD_lazy2 }, /* level 8 */
36 { 22, 20, 21, 4, 5, 16, ZSTD_lazy2 }, /* level 9 */
37 { 22, 21, 22, 5, 5, 16, ZSTD_lazy2 }, /* level 10 */
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This…
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cach…
49 …ress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss i…
56 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
63 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/linux/arch/arm/
H A DKconfig.debug112 bool "Kernel low-level debugging functions (read help!)"
125 prompt "Kernel low-level debugging port"
129 bool "Kernel low-level debugging messages via Alpine UART0"
133 Say Y here if you want kernel low-level debugging support
137 bool "Kernel low-level debugging via asm9260 UART"
158 bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
162 Say Y here if you want kernel low-level debugging support
168 bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
172 Say Y here if you want kernel low-level debugging support
178 bool "Kernel low-level debugging on SAMA5D2 UART1"
[all …]
/linux/fs/xfs/scrub/
H A Dbtree.c29 int level, in __xchk_btree_process_error() argument
53 trace_xchk_ifork_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
56 trace_xchk_btree_op_error(sc, cur, level, in __xchk_btree_process_error()
67 int level, in xchk_btree_process_error() argument
70 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_process_error()
78 int level, in xchk_btree_xref_process_error() argument
81 return __xchk_btree_process_error(sc, cur, level, error, in xchk_btree_xref_process_error()
90 int level, in __xchk_btree_set_corrupt() argument
97 trace_xchk_ifork_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
100 trace_xchk_btree_error(sc, cur, level, in __xchk_btree_set_corrupt()
[all …]
H A Ddabtree.c32 int level, in xchk_da_process_error() argument
57 ds->state->path.blk[level].blkno), in xchk_da_process_error()
71 int level) in xchk_da_set_corrupt() argument
79 ds->state->path.blk[level].blkno), in xchk_da_set_corrupt()
87 int level) in xchk_da_set_preen() argument
94 ds->state->path.blk[level].blkno), in xchk_da_set_preen()
98 /* Find an entry at a certain level in a da btree. */
102 int level) in xchk_da_btree_node_entry() argument
104 struct xfs_da_state_blk *blk = &ds->state->path.blk[level]; in xchk_da_btree_node_entry()
117 int level, in xchk_da_btree_hash() argument
[all …]
/linux/arch/s390/include/asm/
H A Ddebug.h19 #define DEBUG_OFF_LEVEL -1 /* level where debug is switched off */
23 #define DEBUG_DEFAULT_LEVEL 3 /* initial debug level */
35 unsigned long level : 3; member
49 int level; member
106 debug_entry_t *debug_event_common(debug_info_t *id, int level,
109 debug_entry_t *debug_exception_common(debug_info_t *id, int level,
134 * level would be logged. Otherwise returns false.
137 * @level: debug level
140 * - %true if level is less or equal to the current debug level.
142 static inline bool debug_level_enabled(debug_info_t *id, int level) in debug_level_enabled() argument
[all …]
/linux/security/selinux/ss/
H A Dcontext.h47 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy()
48 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy()
52 dst->range.level[1].sens = src->range.level[1].sens; in mls_context_cpy()
53 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[1].cat); in mls_context_cpy()
55 ebitmap_destroy(&dst->range.level[0].cat); in mls_context_cpy()
61 * Sets both levels in the MLS range of 'dst' to the low level of 'src'.
68 dst->range.level[0].sens = src->range.level[0].sens; in mls_context_cpy_low()
69 rc = ebitmap_cpy(&dst->range.level[0].cat, &src->range.level[0].cat); in mls_context_cpy_low()
73 dst->range.level[1].sens = src->range.level[0].sens; in mls_context_cpy_low()
74 rc = ebitmap_cpy(&dst->range.level[1].cat, &src->range.level[0].cat); in mls_context_cpy_low()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a78000.dtsi146 next-level-cache = <&L2_CA720_0>;
153 next-level-cache = <&L2_CA720_1>;
160 next-level-cache = <&L2_CA720_2>;
167 next-level-cache = <&L2_CA720_3>;
174 next-level-cache = <&L2_CA720_4>;
181 next-level-cache = <&L2_CA720_5>;
188 next-level-cache = <&L2_CA720_6>;
195 next-level-cache = <&L2_CA720_7>;
202 next-level-cache = <&L2_CA720_8>;
209 next-level-cache = <&L2_CA720_9>;
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]
/linux/arch/sparc/kernel/
H A Dcpumap.c26 /* Increment rover every time level is visited */
34 int level; member
43 int start_index; /* Index of first node of a level in a cpuinfo tree */
44 int end_index; /* Index of last node of a level in a cpuinfo tree */
45 int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
51 /* Offsets into nodes[] for each level of the tree */
52 struct cpuinfo_level level[CPUINFO_LVL_MAX]; member
96 static int cpuinfo_id(int cpu, int level) in cpuinfo_id() argument
100 switch (level) { in cpuinfo_id()
121 * end index, and number of nodes for each level in the cpuinfo tree. The
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …"PublicDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from…
114 …"BriefDescription": "Level 1 data cache refill started due to prefetch. Counts any linefills from …
117 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
120 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
123 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
126 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Dtraps.h46 #define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
47 #define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
48 #define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
49 #define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
50 #define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
51 #define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
52 #define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
53 #define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
54 #define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
55 #define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/
H A Dl2_cache.json4 …level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction acce…
8 …refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses…
16 …"PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the …
20 …level 2 cache due to instruction accesses. Level 2 cache is a unified cache for data and instructi…
24 …refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses…
28 …level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for da…
32 …level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data a…
36 …ounted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, access…
40 …ounted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, access…
44 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
[all …]
/linux/arch/arm/kernel/
H A Dcacheinfo.c19 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) argument
20 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) argument
21 #define CLIDR_CTYPE(clidr, level) \ argument
22 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
24 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
64 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
68 if (level > MAX_CACHE_LEVEL) in get_cache_type()
73 return CLIDR_CTYPE(clidr, level); in get_cache_type()
77 enum cache_type type, unsigned int level) in ci_leaf_init() argument
79 this_leaf->level = level; in ci_leaf_init()
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/
H A Dl2_cache.json4 …level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction acce…
8 …refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses…
16 …level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for da…
20 …level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data a…
24 …ounted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, access…
28 …ounted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, access…
32 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
36 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
40 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
43 …"PublicDescription": "Counts level 2 cache accesses due to level 1 data cache hardware prefetcher.…
[all …]
/linux/arch/arm64/kernel/
H A Dcacheinfo.c13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
24 static inline enum cache_type get_cache_type(int level) in get_cache_type() argument
28 if (level > MAX_CACHE_LEVEL) in get_cache_type()
31 return CLIDR_CTYPE(clidr, level); in get_cache_type()
35 enum cache_type type, unsigned int level) in ci_leaf_init() argument
37 this_leaf->level = level; in ci_leaf_init()
43 unsigned int ctype, level, leaves; in detect_cache_level() local
45 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { in detect_cache_level()
46 ctype = get_cache_type(level); in detect_cache_level()
48 level--; in detect_cache_level()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
21 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
35 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
49 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w…
56 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache…
63 …"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in…
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi23 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
29 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
35 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
41 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
47 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
53 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
59 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
65 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
71 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
77 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105 …"PublicDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from t…
108 …"BriefDescription": "Level 3 cache refill due to prefetch. This event counts any linefills from th…
111 …"PublicDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a …
114 …"BriefDescription": "Level 2 cache refill due to prefetch. +//0 If the core is configured with a p…
117 …"PublicDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills f…
120 …"BriefDescription": "Level 1 data cache refill due to prefetch. This event counts any linefills fr…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c23 /* offset=13 */ "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-conf…
24 /* offset=99 */ "l1-dcache-load\000legacy cache\000Level 1 data cache read accesses\000legacy-cache…
25 /* offset=190 */ "l1-dcache-load-refs\000legacy cache\000Level 1 data cache read accesses\000legacy…
26 /* offset=286 */ "l1-dcache-load-reference\000legacy cache\000Level 1 data cache read accesses\000l…
27 /* offset=387 */ "l1-dcache-load-ops\000legacy cache\000Level 1 data cache read accesses\000legacy-…
28 /* offset=482 */ "l1-dcache-load-access\000legacy cache\000Level 1 data cache read accesses\000lega…
29 /* offset=580 */ "l1-dcache-load-misses\000legacy cache\000Level 1 data cache read misses\000legacy…
30 /* offset=682 */ "l1-dcache-load-miss\000legacy cache\000Level 1 data cache read misses\000legacy-c…
31 /* offset=782 */ "l1-dcache-loads\000legacy cache\000Level 1 data cache read accesses\000legacy-cac…
32 /* offset=874 */ "l1-dcache-loads-refs\000legacy cache\000Level 1 data cache read accesses\000legac…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
21 …he data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on th…
28 …was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-me…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …ption": "A directory write to the Level-1 Data cache directory where the returned cache line was s…
56 …ruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cach…
63 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa…
70 …Description": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
77 …e Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
84 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
[all …]

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