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/qemu/hw/gpio/
H A Dpca9552.c2 * PCA9552 I2C LED blinker
4 * https://www.nxp.com/docs/en/application-note/AN264.pdf
6 * Copyright (c) 2017-2018, IBM Corporation.
7 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 * later. See the COPYING file in the top-level directory.
17 #include "hw/qdev-properties.h"
54 uint8_t reg = PCA9552_LS0 + (pin / 4); in pca955x_pin_get_config()
55 uint8_t shift = (pin % 4) << 1; in pca955x_pin_get_config()
57 return extract32(s->regs[reg], shift, 2); in pca955x_pin_get_config()
63 return (s->regs[PCA9552_INPUT1] << 8) | s->regs[PCA9552_INPUT0]; in pca955x_pins_get_status()
[all …]
/qemu/hw/display/
H A Djazz_led.c2 * QEMU JAZZ LED emulator.
4 * Copyright (c) 2007-2012 Herve Poussineau
38 #define TYPE_JAZZ_LED "jazz-led"
56 val = s->segments; in jazz_led_read()
70 s->segments = new_val; in jazz_led_write()
71 s->state |= REDRAW_SEGMENTS; in jazz_led_write()
107 case 4: in draw_horizontal_line()
110 d += 4; in draw_horizontal_line()
138 case 4: in draw_vertical_line()
150 DisplaySurface *surface = qemu_console_surface(s->con); in jazz_led_update_display()
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H A Dtrace-events27 vmware_update_rect_delayed_flush(void) "display update FIFO full - forcing flush"
29 # virtio-gpu-base.c
32 # virtio-gpu-3d.c
33 # virtio-gpu.c
56 virtio_gpu_inc_inflight_fences(uint32_t inflight) "in-flight+ %u"
57 virtio_gpu_dec_inflight_fences(uint32_t inflight) "in-flight- %u"
81 …_t slot_id, uint64_t guest_start, uint64_t guest_end) "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64
121 # qxl-render.c
145 ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s -…
146 …unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64
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/qemu/hw/misc/
H A Dmps2-scc.c29 #include "hw/misc/mps2-scc.h"
30 #include "hw/misc/led.h"
31 #include "hw/qdev-properties.h"
34 REG32(CFG1, 4)
47 FIELD(CFGCTRL, RES2, 26, 4)
60 return extract32(s->id, 4, 8); in scc_partno()
116 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_write()
123 s->oscclk[device] = value; in scc_cfg_write()
134 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_read()
141 *value = s->oscclk[device]; in scc_cfg_read()
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H A Dmps2-fpgaio.c26 #include "hw/misc/mps2-fpgaio.h"
27 #include "hw/misc/led.h"
28 #include "hw/qdev-properties.h"
32 REG32(DBGCTRL, 4)
44 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); in counter_from_tickoff()
49 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); in tickoff_from_counter()
55 * Update s->counter and s->pscntr to their true current values in resync_counter()
60 int64_t elapsed = now - s->pscntr_sync_ticks; in resync_counter()
66 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); in resync_counter()
70 * PSCNTR reloads from PRESCALE one tick-period after it hits zero, in resync_counter()
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H A Darm_sysctl.c4 * Copyright (c) 2006-2007 CodeSourcery.
12 #include "hw/qdev-properties.h"
58 .version_id = 4,
73 VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
75 4, vmstate_info_uint32, uint32_t),
93 return (s->sys_id >> 16) & 0xfff; in board_id()
101 s->leds = 0; in arm_sysctl_reset()
102 s->lockval = 0; in arm_sysctl_reset()
103 s->cfgdata1 = 0; in arm_sysctl_reset()
104 s->cfgdata2 = 0; in arm_sysctl_reset()
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/qemu/hw/pci/
H A Dshpc.c3 #include "qemu/host-utils.h"
5 #include "qemu/error-report.h"
7 #include "migration/qemu-file-types.h"
17 /* TODO: remove fully only on state DISABLED and LED off.
21 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
22 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
23 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */
47 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
49 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
50 #define SHPC_SERR_INT 0x20 /* 4 bytes */
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/qemu/include/hw/gpio/
H A Dpca9552_regs.h2 * PCA9552 I2C LED blinker registers
4 * Copyright (c) 2017-2018, IBM Corporation.
7 * later. See the COPYING file in the top-level directory.
19 #define PCA9552_PSC1 4 /* read/write frequency prescaler 1 */
27 * Bit [4] is used to activate the Auto-Increment option of the
30 #define PCA9552_AUTOINC (1 << 4)
/qemu/hw/net/
H A De1000_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
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H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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/qemu/hw/m68k/
H A Dnext-cube.c5 * Copyright (c) 2024 Mark Cave-Ayland
15 #include "exec/cpu-interrupt.h"
19 #include "hw/m68k/next-cube.h"
28 #include "hw/qdev-properties.h"
30 #include "qemu/error-report.h"
48 #define TYPE_NEXT_RTC "next-rtc"
66 #define TYPE_NEXT_SCSI "next-scsi"
82 #define TYPE_NEXT_PC "next-pc"
102 uint32_t led; member
133 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
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/qemu/hw/input/
H A Dhid.c77 return hs->n > 0 || hs->idle_pending; in hid_has_events()
84 hs->idle_pending = true; in hid_idle_timer()
85 hs->event(hs); in hid_idle_timer()
90 if (hs->idle_timer) { in hid_del_idle_timer()
91 timer_free(hs->idle_timer); in hid_del_idle_timer()
92 hs->idle_timer = NULL; in hid_del_idle_timer()
98 if (hs->idle) { in hid_set_next_idle()
100 NANOSECONDS_PER_SECOND * hs->idle * 4 / 1000; in hid_set_next_idle()
101 if (!hs->idle_timer) { in hid_set_next_idle()
102 hs->idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hid_idle_timer, hs); in hid_set_next_idle()
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/qemu/hw/mips/
H A Djazz.c4 * Copyright (c) 2007-2008 Hervé Poussineau
31 #include "hw/char/serial-mm.h"
43 #include "hw/display/bochs-vbe.h"
50 #include "qemu/error-report.h"
53 #include "accel/tcg/cpu-ops.h"
139 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
145 prom[i] = nd->macaddr.a[i]; in mips_jazz_init_net()
151 prom[7] = 0xff - checksum; in mips_jazz_init_net()
154 #define BIOS_SIZE (4 * MiB)
198 [JAZZ_PICA61] = {33333333, 4}, in mips_jazz_init()
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/qemu/include/hw/ppc/
H A Dspapr_drc.h10 * See the COPYING file in the top-level directory.
19 #include "hw/qdev-core.h"
22 #define TYPE_SPAPR_DR_CONNECTOR "spapr-dr-connector"
31 #define TYPE_SPAPR_DRC_PHYSICAL "spapr-drc-physical"
35 #define TYPE_SPAPR_DRC_LOGICAL "spapr-drc-logical"
37 #define TYPE_SPAPR_DRC_CPU "spapr-drc-cpu"
39 #define TYPE_SPAPR_DRC_PCI "spapr-drc-pci"
41 #define TYPE_SPAPR_DRC_LMB "spapr-drc-lmb"
43 #define TYPE_SPAPR_DRC_PHB "spapr-drc-phb"
45 #define TYPE_SPAPR_DRC_PMEM "spapr-drc-pmem"
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/qemu/hw/arm/
H A Dintegratorcp.c4 * Copyright (c) 2005-2007 CodeSourcery.
19 #include "system/address-spaces.h"
23 #include "qemu/error-report.h"
30 #include "target/arm/cpu-qom.h"
58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
98 return s->cm_osc; in integratorcm_read()
100 return s->cm_ctrl; in integratorcm_read()
101 case 4: /* CM_STAT */ in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
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H A Daspeed.c9 * the COPYING file in the top-level directory.
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "system/block-backend.h"
29 #include "qemu/error-report.h"
32 #include "hw/qdev-clock.h"
36 .board_id = -1, /* device-tree-only board */
53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
166 /* Quanta-Q71l hardware value */
204 /* Qualcomm DC-SCM hardware value */
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H A Domap1.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
26 #include "system/address-spaces.h"
29 #include "hw/qdev-properties.h"
44 #include "target/arm/cpu-qom.h"
49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
94 omap_log_badwidth(__func__, addr, 4); in omap_badwidth_read32()
95 cpu_physical_memory_read(addr, &ret, 4); in omap_badwidth_read32()
102 omap_log_badwidth(__func__, addr, 4); in omap_badwidth_write32()
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/qemu/include/hw/misc/macio/
H A Dpmu.h25 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
26 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
27 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
28 #define PMU_SET_RTC 0x30 /* set real-time clock */
29 #define PMU_READ_RTC 0x38 /* read real-time clock */
33 #define PMU_PCEJECT 0x4c /* eject PC-card from slot */
41 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
62 #define PMU_POW_IRLED 0x04 /* IR led power (on wallstreet) */
67 #define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
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/qemu/linux-user/
H A Dsyscall_defs.h17 #define TARGET_SYS_LISTEN 4 /* listen() */
39 #define IPCOP_semtimedop 4
95 #define TARGET_IOC_WRITE 4U
118 #define TARGET_IOC_NRMASK ((1 << TARGET_IOC_NRBITS)-1)
119 #define TARGET_IOC_TYPEMASK ((1 << TARGET_IOC_TYPEBITS)-1)
120 #define TARGET_IOC_SIZEMASK ((1 << TARGET_IOC_SIZEBITS)-1)
121 #define TARGET_IOC_DIRMASK ((1 << TARGET_IOC_DIRBITS)-1)
180 uint8_t __pad[sizeof(struct target_sockaddr) -
181 sizeof(abi_ushort) - sizeof(abi_short) -
283 abi_long constant; /* PLL (phase-locked loop) time constant */
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/qemu/include/hw/arm/
H A Domap.h4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
24 #include "target/arm/cpu-qom.h"
62 #define TYPE_OMAP_INTC "omap-intc"
94 #define TYPE_OMAP1_GPIO "omap-gpio"
104 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
130 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
137 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
139 #define OMAP_INT_1510_SPI_TX 4
145 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
147 #define OMAP_INT_310_McBSP2_TX 4
[all …]
/qemu/ui/
H A Dvnc.h38 #include "io/channel-socket.h"
39 #include "io/channel-tls.h"
40 #include "io/net-listener.h"
45 #include "vnc-palette.h"
46 #include "vnc-enc-zrle.h"
47 #include "ui/kbd-state.h"
92 #define VNC_DIRTY_BPL(x) (sizeof((x)->dirty) / VNC_MAX_HEIGHT * BITS_PER_BYTE)
102 #include "vnc-auth-vencrypt.h"
104 #include "vnc-auth-sasl.h"
106 #include "vnc-ws.h"
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H A Dvnc.c29 #include "vnc-jobs.h"
31 #include "hw/qdev-core.h"
34 #include "qemu/error-report.h"
35 #include "qemu/main-loop.h"
41 #include "qemu/config-file.h"
42 #include "qapi/qapi-emit-events.h"
43 #include "qapi/qapi-events-ui.h"
45 #include "qapi/qapi-commands-ui.h"
56 #include "io/dns-resolver.h"
84 fprintf(stderr, "%s/%p: %s -> %s\n", __func__, in vnc_set_share_mode()
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/qemu/hw/sd/
H A Dsdhci.c10 * Based on MMC controller for Samsung S5PC1xx-based board emulation
29 #include "qemu/error-report.h"
32 #include "hw/qdev-properties.h"
38 #include "sdhci-internal.h"
43 #define TYPE_SDHCI_BUS "sdhci-bus"
52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()
59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()
68 "in range 0-63 only", desc); in sdhci_check_capab_freq_range()
76 uint64_t msk = s->capareg; in sdhci_check_capareg()
80 switch (s->sd_spec_version) { in sdhci_check_capareg()
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/qemu/hw/char/
H A Descc.c4 * Copyright (c) 2003-2005 Fabrice Bellard
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
45 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
70 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
74 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
77 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
100 #define W_TXCTRL1 4
181 #define R_IPEN 4
202 return s->bit_swap ? s->it_shift + 1 : s->it_shift; in reg_shift()
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/qemu/qapi/
H A Dmachine.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
12 { 'include': 'machine-common.json' }
18 # targets. Run "./configure --help" in the project root directory,
19 # and look for the \*-softmmu targets near the "--target-list" option.
30 # "qemu-system-" prefix to produce the corresponding QEMU
31 # executable name. This is true even for "qemu-system-x86_64".
52 'data': [ 'uninitialized', 'stopped', 'check-stop', 'operating', 'load' ] }
59 # @cpu-state: the virtual CPU's state
68 'data': { 'cpu-state': 'S390CpuState',
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