| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 113 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
114 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
115 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
116 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
118 /* SERDES4 lane0/1/2/3 select */
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | analogix,anx7625.yaml | 45 analogix,lane0-swing:
50 an array of swing register setting for DP tx lane0 PHY.
78 DP TX lane1 swing register setting same with lane0
79 swing, please refer lane0-swing property description.
149 analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 64 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
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| H A D | airoha,en7581-pcie-phy.yaml | 22 - description: PCIE lane0 base address
24 - description: PCIE lane0 detection time base address
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| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 87 - lane0
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| H A D | fsl,imx8qm-hsio.yaml | 55 | | Lane0| Lane1| Lane2|
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-dwc-pcie | 6 selected lane. The default selected lane is Lane0.
13 selected lane. The default selected lane is Lane0.
151 selected lane number. Lane0 is selected by default.
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8qm-hsio.c | 370 * Except the phy_off, the bit-offset of lane2 is same to lane0. in imx_hsio_power_on()
371 * Merge the lane0 and lane2 bit-operations together. in imx_hsio_power_on()
433 * to lane0. Merge the lane0 and lane2 bit-operations in imx_hsio_power_off()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
262 - const: phy-lane0
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| /linux/arch/arm64/boot/dts/airoha/ |
| H A D | en7581.dtsi | 223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j722s-main.dtsi | 417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
418 <0x10 0x3>; /* SERDES1 lane0 select */
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| H A D | k3-j721e-main.dtsi | 71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
72 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
73 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
74 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
75 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
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| H A D | k3-j784s4-j742s2-main-common.dtsi | 82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
|
| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 187 * lane0: USB3/GbE1 PHY Configuration 1
208 * lane0: USB3/GbE1 PHY Status 1
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8186-corsola-steelix.dtsi | 63 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
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| H A D | mt8186-corsola-chinchou.dtsi | 72 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
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| /linux/drivers/phy/starfive/ |
| H A D | phy-jh7110-dphy-rx.c | 56 * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-friendlyelec-cm3588-nas.dts | 458 /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */
469 /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */
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| H A D | rk3568.dtsi | 245 /* bifurcation; lane0 when using 1+1 */
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| H A D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
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| /linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 242 uint8_t lane0:2; /* Mapping for lane 0 */ member
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| /linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | dsi.xml | 98 <bitfield name="LANE0" pos="4" type="boolean"/>
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| /linux/drivers/phy/ti/ |
| H A D | phy-j721e-wiz.c | 65 LANE0 = 0, enumerator
1282 case LANE0: in wiz_phy_reset_deassert()
|