Searched +full:k210 +full:- +full:sram (Results 1 – 4 of 4) sorted by relevance
/linux-6.8/Documentation/devicetree/bindings/memory-controllers/ |
D | canaan,k210-sram.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Canaan K210 SRAM memory controller 10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB 11 of SRAM. The controller is initialised by the bootloader, which configures 15 - Conor Dooley <conor@kernel.org> 20 - canaan,k210-sram 25 - description: sram0 clock [all …]
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/linux-6.8/drivers/soc/canaan/ |
D | k210-sysctl.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 #include <soc/canaan/k210-sysctl.h> 16 struct device *dev = &pdev->dev; in k210_sysctl_probe() 20 dev_info(dev, "K210 system controller\n"); in k210_sysctl_probe() 43 { .compatible = "canaan,k210-sysctl", }, 49 .name = "k210-sysctl", 64 * PLL1 needs to be enabled to be able to use all SRAM. 72 panic("k210-sysctl: ioremap failed"); in k210_soc_early_init() 78 SOC_EARLY_INIT_DECLARE(k210_soc, "canaan,kendryte-k210", k210_soc_early_init);
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/linux-6.8/arch/riscv/boot/dts/canaan/ |
D | k210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 6 #include <dt-bindings/clock/k210-clk.h> 7 #include <dt-bindings/pinctrl/k210-fpioa.h> 8 #include <dt-bindings/reset/k210-rst.h> 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 27 * The K210 has an sv39 MMU following the privileged specification v1.9. [all …]
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/linux-6.8/drivers/clk/ |
D | clk-k210.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 6 #define pr_fmt(fmt) "k210-clk: " fmt 15 #include <linux/clk-provider.h> 18 #include <soc/canaan/k210-sysctl.h> 20 #include <dt-bindings/clock/k210-clk.h> 301 * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0 302 * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the 322 * struct k210_sysclk - sysclk driver data 356 pll->id = pllid; in k210_init_pll() [all …]
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