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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmstar,mst-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
21 const: mstar,mst-intc
23 interrupt-controller: true
25 "#interrupt-cells":
33 mstar,irqs-map-range:
35 The range <start, end> of parent interrupt controller's interrupt
[all …]
/linux-5.10/Documentation/core-api/irq/
Dirq-domain.rst9 that each one gets assigned non-overlapping allocations of Linux
24 For this reason we need a mechanism to separate controller-local
29 the controller-local IRQ (hwirq) number into the Linux IRQ number
55 the hwirq, and call the .map() callback so the driver can perform any
67 callbacks) then it can be directly obtained from irq_data->hwirq.
74 Which reverse map type should be used depends on the use case. Each
75 of the reverse map types are described below:
78 ------
85 The linear reverse map maintains a fixed size table indexed by the
89 The Linear map is a good choice when the maximum number of hwirqs is
[all …]
/linux-5.10/arch/sparc/kernel/
Dof_device_64.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-mapping.h>
20 unsigned long ret = res->start + offset; in of_ioremap()
23 if (res->flags & IORESOURCE_MEM) in of_ioremap()
36 if (res->flags & IORESOURCE_MEM) in of_iounmap()
58 * parent as-is, not with the PCI translate in of_bus_pci_match()
88 static int of_bus_simba_map(u32 *addr, const u32 *range, in of_bus_simba_map() argument
103 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
110 if (!((addr[0] ^ range[0]) & 0x03000000)) in of_bus_pci_map()
113 /* Special exception, we can map a 64-bit address into in of_bus_pci_map()
[all …]
Dof_device_32.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-mapping.h>
29 * parent as-is, not with the PCI translate in of_bus_pci_match()
50 static int of_bus_pci_map(u32 *addr, const u32 *range, in of_bus_pci_map() argument
57 if ((addr[0] ^ range[0]) & 0x03000000) in of_bus_pci_map()
58 return -EINVAL; in of_bus_pci_map()
60 if (of_out_of_range(addr + 1, range + 1, range + na + pna, in of_bus_pci_map()
61 na - 1, ns)) in of_bus_pci_map()
62 return -EINVAL; in of_bus_pci_map()
64 /* Start with the parent range base. */ in of_bus_pci_map()
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/linux-5.10/arch/arm/boot/dts/
Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
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/linux-5.10/drivers/soc/ti/
Dknav_qmss_queue.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
42 * are to be re-defined
55 (kdev->instances + (idx << kdev->inst_shift))
58 list_for_each_entry_rcu(qh, &inst->handles, list, \
62 for (idx = 0, inst = kdev->instances; \
63 idx < (kdev)->num_queues_in_use; \
93 if (atomic_read(&qh->notifier_enabled) <= 0) in knav_queue_notify()
95 if (WARN_ON(!qh->notifier_fn)) in knav_queue_notify()
[all …]
/linux-5.10/include/linux/gpio/
Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
29 * struct gpio_irq_chip - GPIO interrupt controller
66 * If non-NULL, will be set as the parent of this GPIO interrupt
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
135 * GPIO IRQs, provided by GPIO driver.
193 * @map:
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/linux-5.10/drivers/irqchip/
Dirq-mst-intc.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
4 * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
37 raw_spin_lock_irqsave(&cd->lock, flags); in mst_set_irq()
38 val = readw_relaxed(cd->base + offset) | mask; in mst_set_irq()
39 writew_relaxed(val, cd->base + offset); in mst_set_irq()
40 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_set_irq()
53 raw_spin_lock_irqsave(&cd->lock, flags); in mst_clear_irq()
54 val = readw_relaxed(cd->base + offset) & ~mask; in mst_clear_irq()
55 writew_relaxed(val, cd->base + offset); in mst_clear_irq()
56 raw_spin_unlock_irqrestore(&cd->lock, flags); in mst_clear_irq()
[all …]
Dirq-ti-sci-inta.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
24 #include <asm-generic/msi.h>
44 * struct ti_sci_inta_event_desc - Description of an event coming to
59 * struct ti_sci_inta_vint_desc - Description of a virtual interrupt coming out
78 * struct ti_sci_inta_irq_domain - Structure representing a TISCI based
87 * @ti_sci_id: TI-SCI device identifier
89 * @unmapped_dev_ids: Pointer to an array of TI-SCI device identifiers of
91 * Unmapped Events are not part of the Global Event Map and
95 * generating Unmapped Event, we must use the INTA's TI-SCI
[all …]
Dirq-i8259.c6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
9 * Copyright (C) 1994 - 2000 Ralf Baechle
35 static int i8259A_auto_eoi = -1;
44 .name = "XT-PIC",
70 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; in disable_8259A_irq()
85 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; in enable_8259A_irq()
136 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; in mask_and_ack_8259A()
143 * to overdo spurious IRQ handling - it's usually a sign in mask_and_ack_8259A()
147 * Note that IRQ7 and IRQ15 (the two spurious IRQs in mask_and_ack_8259A()
148 * usually resulting from the 8259A-1|2 PICs) occur in mask_and_ack_8259A()
[all …]
/linux-5.10/kernel/irq/
Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
49 * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
54 * @pa: Optional user-provided physical address
78 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
91 fwid->type = type; in __irq_domain_alloc_fwnode()
92 fwid->name = n; in __irq_domain_alloc_fwnode()
93 fwid->pa = pa; in __irq_domain_alloc_fwnode()
94 fwid->fwnode.ops = &irqchip_fwnode_ops; in __irq_domain_alloc_fwnode()
95 return &fwid->fwnode; in __irq_domain_alloc_fwnode()
100 * irq_domain_free_fwnode - Free a non-OF-backed fwnode_handle
[all …]
/linux-5.10/arch/mips/ralink/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
29 /* we have a cascade of 8 irqs */
32 /* we have 32 SoC irqs */
71 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE); in ralink_intc_irq_unmask()
76 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE); in ralink_intc_irq_mask()
143 .map = intc_map,
153 if (!of_property_read_u32_array(node, "ralink,intc-registers", in intc_of_init()
155 pr_info("intc: using register map from devicetree\n"); in intc_of_init()
162 panic("Failed to get intc memory range"); in intc_of_init()
195 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
[all …]
/linux-5.10/drivers/pinctrl/
Dpinctrl-single.c29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
117 * struct pcs_data - wrapper for data needed by pinctrl framework
131 * struct pcs_soc_data - SoC specific settings
[all …]
/linux-5.10/arch/powerpc/platforms/52xx/
Dmpc52xx_pic.c23 * -----------------
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
39 * a unique range of the global IRQ# space.
41 * To define a range of virq numbers for this controller, this driver first
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
74 * register even though one of the external IRQs is in the critical group and
[all …]
/linux-5.10/arch/powerpc/platforms/embedded6xx/
Dhlwd-pic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
9 #define DRV_MODULE_NAME "hlwd-pic"
19 #include "hlwd-pic.h"
81 .name = "hlwd-pic",
98 irq_set_chip_data(virq, h->host_data); in hlwd_pic_map()
105 .map = hlwd_pic_map,
110 void __iomem *io_base = h->host_data; in __hlwd_pic_get_irq()
117 return 0; /* no more IRQs pending */ in __hlwd_pic_get_irq()
129 raw_spin_lock(&desc->lock); in hlwd_pic_irq_cascade()
[all …]
Dflipper-pic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/powerpc/platforms/embedded6xx/flipper-pic.c
6 * Copyright (C) 2004-2009 The GameCube Linux Team
9 #define DRV_MODULE_NAME "flipper-pic"
19 #include "flipper-pic.h"
83 .name = "flipper-pic",
100 irq_set_chip_data(virq, h->host_data); in flipper_pic_map()
107 .map = flipper_pic_map,
117 /* mask and ack all IRQs */ in __flipper_quiesce()
135 if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) { in flipper_pic_init()
[all …]
/linux-5.10/arch/mips/lantiq/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
22 /* register definitions - internal irqs */
31 /* register definitions - external irqs */
44 * irqs generated by devices attached to the EBU need to be acked in
58 /* we have a cascade of 8 irqs */
74 return -1; in ltq_eiu_get_irq()
79 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq()
97 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq()
116 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_ack_irq()
132 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_enable_irq()
[all …]
/linux-5.10/drivers/staging/mt7621-pci/
Dpci-mt7621.c1 // SPDX-License-Identifier: GPL-2.0+
49 /* Host-PCI bridge registers */
92 * struct mt7621_pcie_port - PCIe port information
116 * struct mt7621_pcie - PCIe host information
119 * @mem: non-prefetchable memory resource
120 * @busn: bus range
147 return readl(pcie->base + reg); in pcie_read()
152 writel(val, pcie->base + reg); in pcie_write()
157 u32 val = readl(pcie->base + reg); in pcie_rmw()
161 writel(val, pcie->base + reg); in pcie_rmw()
[all …]
/linux-5.10/drivers/gpio/
Dgpio-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0
9 * linux/arch/arm/mach-ep93xx/core.c
32 * Static mapping of GPIO bank F IRQS:
43 * Interrupt handling for EP93xx on-chip GPIOs
62 writeb_relaxed(0, epg->base + int_en_register_offset[port]); in ep93xx_gpio_update_int_params()
65 epg->base + int_type2_register_offset[port]); in ep93xx_gpio_update_int_params()
68 epg->base + int_type1_register_offset[port]); in ep93xx_gpio_update_int_params()
71 epg->base + int_en_register_offset[port]); in ep93xx_gpio_update_int_params()
79 while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port]) in ep93xx_gpio_port()
83 if (port == ARRAY_SIZE(epg->gc)) { in ep93xx_gpio_port()
[all …]
/linux-5.10/drivers/pnp/
Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
9 * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
34 dev_err(&dev->dev, "couldn't add ioport region to option set " in quirk_awe32_add_ports()
40 new_option->u.port.min += offset; in quirk_awe32_add_ports()
41 new_option->u.port.max += offset; in quirk_awe32_add_ports()
42 list_add(&new_option->list, &option->list); in quirk_awe32_add_ports()
44 dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n", in quirk_awe32_add_ports()
45 (unsigned long long) new_option->u.port.min, in quirk_awe32_add_ports()
46 (unsigned long long) new_option->u.port.max, in quirk_awe32_add_ports()
[all …]
/linux-5.10/drivers/scsi/cxlflash/
Docxl_hw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 * Pseudo-filesystem to allocate inodes.
38 return init_pseudo(fc, OCXLFLASH_FS_MAGIC) ? 0 : -ENOMEM; in ocxlflash_fs_init_fs_context()
49 * ocxlflash_release_mapping() - release the memory mapping
54 if (ctx->mapping) in ocxlflash_release_mapping()
56 ctx->mapping = NULL; in ocxlflash_release_mapping()
60 * ocxlflash_getfile() - allocate pseudo filesystem, inode, and the file
77 if (fops->owner && !try_module_get(fops->owner)) { in ocxlflash_getfile()
79 rc = -ENOENT; in ocxlflash_getfile()
91 inode = alloc_anon_inode(ocxlflash_vfs_mount->mnt_sb); in ocxlflash_getfile()
[all …]
/linux-5.10/arch/ia64/
DMakefile5 # architecture-specific flags and dependencies.
11 # Copyright (C) 1998-2004 by David Mosberger-Tang <davidm@hpl.hp.com>
16 NM := $(CROSS_COMPILE)nm -B
19 CHECKFLAGS += -D__ia64=1 -D__ia64__=1 -D_LP64 -D__LP64__
21 OBJCOPYFLAGS := --strip-all
22 LDFLAGS_vmlinux := -static
23 KBUILD_AFLAGS_KERNEL := -mconstant-gp
26 cflags-y := -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f12-f15,f32-f127 \
27 -falign-functions=32 -frename-registers -fno-optimize-sibling-calls
28 KBUILD_CFLAGS_KERNEL := -mconstant-gp
[all …]
/linux-5.10/include/linux/
Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Register map access API
48 * struct reg_default - Default value for a register.
62 * struct reg_sequence - An individual write from a sequence of writes.
85 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
87 * @map: Regmap to read from
92 * tight-loops). Should be less than ~20ms since usleep_range
93 * is used (see Documentation/timers/timers-howto.rst).
96 * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
103 #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \ argument
[all …]
/linux-5.10/arch/arm/mach-mmp/
Djasper.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/jasper.c
7 * Copyright (C) 2009-2010 Marvell International Ltd.
12 #include <linux/gpio-pxa.h>
20 #include "irqs.h"
21 #include <asm/mach-types.h>
23 #include "addr-map.h"
24 #include "mfp-mmp2.h"
110 .name = "vcc_core range",
166 /* on-chip devices */ in jasper_init()
/linux-5.10/arch/powerpc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 # On Book3S 64, the default virtual address space for 64-bit processes
20 # between bottom-up and top-down allocations for applications that
23 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
24 default 33 if PPC_BOOK3S_64 # 33 = 45 (32T) - 12 (4K)
26 # On all other 64-bit platforms (currently only Book3E), the virtual
29 default 32 if 64BIT # 32 = 44 (16T) - 12 (4K)
31 # For 32-bit, use the compat values, as they're the same.
36 default 14 if 64BIT && PPC_64K_PAGES # 14 = 30 (1GB) - 16 (64K)
37 default 18 if 64BIT # 18 = 30 (1GB) - 12 (4K)
[all …]

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