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/linux-5.10/drivers/irqchip/
Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
34 u32 type; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
53 * @type: IRQ type
[all …]
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
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/linux-5.10/drivers/parisc/
Diosapic_private.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
35 ** Interrupt Type of 0 indicates a vectored interrupt,
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
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/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 mbox-names = "rx", "tx";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
21 scm_conf: scm-conf@100000 {
22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
24 #address-cells = <1>;
25 #size-cells = <1>;
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Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
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Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
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Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux-5.10/drivers/tty/serial/jsm/
Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
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Djsm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
49 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
70 /* Board type definitions */
94 #define JSM_VERSION "jsm: 1.2-1-INKERNEL"
95 #define JSM_PARTNUM "40002438_A-INKERNEL"
104 irq_handler_t intr; member
124 * Per-board information
128 int boardnum; /* Board number: 0-32 */
130 int type; /* Type of board */ member
183 #define RQUEUEMASK 0x1FFF /* 8 K - 1 */
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/linux-5.10/drivers/net/ethernet/pensando/ionic/
Dionic_dev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
19 mod_timer(&ionic->watchdog_timer, in ionic_watchdog_cb()
20 round_jiffies(jiffies + ionic->watchdog_period)); in ionic_watchdog_cb()
22 if (!ionic->lif) in ionic_watchdog_cb()
28 ionic_link_status_check_request(ionic->lif, false); in ionic_watchdog_cb()
33 struct ionic_dev *idev = &ionic->idev; in ionic_init_devinfo()
35 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); in ionic_init_devinfo()
36 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); in ionic_init_devinfo()
38 memcpy_fromio(idev->dev_info.fw_version, in ionic_init_devinfo()
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/linux-5.10/drivers/mfd/
Dasic3.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
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/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
146 /* NVM Addressing bits based on type 0=small, 1=large */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
218 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
225 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
240 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
244 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
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/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
31 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
34 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
37 (p) ? (p)->parent->base.id : -1, \
38 (p) ? (p)->intf_idx - INTF_0 : -1, \
39 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
43 (p) ? (p)->parent->base.id : -1, \
44 (p) ? (p)->intf_idx - INTF_0 : -1, \
45 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
[all …]
/linux-5.10/arch/x86/kernel/apic/
Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
94 int trigger; member
111 * Saved state during suspend/resume, or while enabling intr-remap.
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
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/linux-5.10/drivers/iio/accel/
Dbmc150-accel-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
4 * - BMC150
5 * - BMI055
6 * - BMA255
7 * - BMA250E
8 * - BMA222E
9 * - BMA280
26 #include <linux/iio/trigger.h>
31 #include "bmc150-accel.h"
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/linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_pf.c1 // SPDX-License-Identifier: GPL-2.0
27 #define DRV_NAME "octeontx2-nicpf"
58 netdev->mtu, new_mtu); in otx2_change_mtu()
59 netdev->mtu = new_mtu; in otx2_change_mtu()
69 int irq, vfs = pf->total_vfs; in otx2_disable_flr_me_intr()
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); in otx2_disable_flr_me_intr()
78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); in otx2_disable_flr_me_intr()
84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in otx2_disable_flr_me_intr()
85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); in otx2_disable_flr_me_intr()
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in otx2_disable_flr_me_intr()
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/linux-5.10/drivers/iommu/intel/
Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
13 #include <linux/intel-iommu.h>
22 #include <asm/pci-direct.h>
71 * ->dmar_global_lock
72 * ->irq_2_ir_lock
73 * ->qi->q_lock
74 * ->iommu->register_lock
77 * in single-threaded environment with interrupt disabled, so no need to tabke
88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
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/linux-5.10/arch/powerpc/include/uapi/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
9 * since we can keep non-volatile in the thread_struct
11 * by intr code.
56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
129 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
132 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
138 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
140 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
146 * The transfer totals 34 quadword. Quadwords 0-31 contain the
153 * structures. This also simplifies the implementation of a bi-arch
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/linux-5.10/arch/mips/kvm/
Dmips.c102 return !!(vcpu->arch.pending_exceptions); in kvm_arch_vcpu_runnable()
117 return kvm_mips_callbacks->hardware_enable(); in kvm_arch_hardware_enable()
122 kvm_mips_callbacks->hardware_disable(); in kvm_arch_hardware_disable()
137 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) in kvm_arch_init_vm() argument
139 switch (type) { in kvm_arch_init_vm()
149 /* Unsupported KVM type */ in kvm_arch_init_vm()
150 return -EINVAL; in kvm_arch_init_vm()
153 /* Allocate page table to map GPA -> RPA */ in kvm_arch_init_vm()
154 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); in kvm_arch_init_vm()
155 if (!kvm->arch.gpa_mm.pgd) in kvm_arch_init_vm()
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/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_nv.c66 return -ENOENT; in xgpu_nv_mailbox_rcv_msg()
89 timeout -= 5; in xgpu_nv_poll_ack()
94 return -ETIME; in xgpu_nv_poll_ack()
107 timeout -= 10; in xgpu_nv_poll_msg()
111 return -ETIME; in xgpu_nv_poll_msg()
153 enum idh_event event = -1; in xgpu_nv_send_access_requests()
170 if (event != -1) { in xgpu_nv_send_access_requests()
178 adev->virt.req_init_data_ver = 0; in xgpu_nv_send_access_requests()
182 adev->virt.req_init_data_ver = in xgpu_nv_send_access_requests()
186 if (adev->virt.req_init_data_ver < 1) in xgpu_nv_send_access_requests()
[all …]
Dmxgpu_ai.c69 return -ENOENT; in xgpu_ai_mailbox_rcv_msg()
91 timeout -= 5; in xgpu_ai_poll_ack()
96 return -ETIME; in xgpu_ai_poll_ack()
109 timeout -= 10; in xgpu_ai_poll_msg()
114 return -ETIME; in xgpu_ai_poll_msg()
179 adev->virt.fw_reserve.checksum_key = in xgpu_ai_send_access_requests()
218 DRM_DEBUG("get ack intr and do nothing.\n"); in xgpu_ai_mailbox_ack_irq()
224 unsigned type, in xgpu_ai_set_mailbox_ack_irq() argument
246 if (!down_read_trylock(&adev->reset_sem)) in xgpu_ai_mailbox_flr_work()
249 atomic_set(&adev->in_gpu_reset, 1); in xgpu_ai_mailbox_flr_work()
[all …]
/linux-5.10/drivers/scsi/bfa/
Dbfa_core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
43 bfa_isr_unhandled, /* --------- */
44 bfa_isr_unhandled, /* --------- */
45 bfa_isr_unhandled, /* --------- */
46 bfa_isr_unhandled, /* --------- */
47 bfa_isr_unhandled, /* --------- */
48 bfa_isr_unhandled, /* --------- */
[all …]
/linux-5.10/arch/microblaze/boot/dts/
Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
[all …]
/linux-5.10/drivers/rtc/
Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
40 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
43 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
44 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
45 #define DCR_KSSL (1 << 27) /* Key-select soft lock */
46 #define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
47 #define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
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