/linux-3.3/arch/powerpc/platforms/86xx/ |
D | gef_pic.c | 2 * Interrupt handling for GE FPGA based PIC 17 #include <linux/interrupt.h> 38 /* Interrupt Controller Interface Registers */ 57 * Interrupt Controller Handling 59 * The interrupt controller handles interrupts for most on board interrupts, 67 * 12 RO Real Time Clock Interrupt Status 68 * 11 RO Temperature Interrupt Status 69 * 10 RO Temperature Critical Interrupt Status 70 * 9 RO Ethernet PHY1 Interrupt Status 71 * 8 RO Ethernet PHY3 Interrupt Status [all …]
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/linux-3.3/include/linux/ |
D | regmap.h | 5 * Register map access API 44 * Configuration for the register map of a device. 57 * (eg, a clear on read interrupt status register). 64 * @read_flag_mask: Mask to be set in the top byte of the register when doing 66 * @write_flag_mask: Mask to be set in the top byte of the register when doing 105 * Description of a hardware bus for the register map infrastructure. 108 * @gather_write: Write operation with split register/value, return -ENOTSUPP 112 * @read_flag_mask: Mask to be set in the top byte of the register when doing 130 void regmap_exit(struct regmap *map); 131 int regmap_reinit_cache(struct regmap *map, [all …]
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/linux-3.3/drivers/base/regmap/ |
D | regmap-irq.c | 16 #include <linux/interrupt.h> 24 struct regmap *map; member 39 return &data->chip->irqs[irq - data->irq_base]; in irq_to_regmap_irq() 46 mutex_lock(&d->lock); in regmap_irq_lock() 55 * If there's been a change in the mask write it back to the in regmap_irq_sync_unlock() 59 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock() 60 ret = regmap_update_bits(d->map, d->chip->mask_base + i, in regmap_irq_sync_unlock() 61 d->mask_buf_def[i], d->mask_buf[i]); in regmap_irq_sync_unlock() 63 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock() 64 d->chip->mask_base + i); in regmap_irq_sync_unlock() [all …]
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/linux-3.3/arch/blackfin/mach-bf548/include/mach/ |
D | defBF54x_base.h | 2 * Copyright 2007-2010 Analog Devices Inc. 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ 31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ 39 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ 40 #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ 41 #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ 42 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ 43 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ [all …]
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/linux-3.3/drivers/pcmcia/ |
D | pd6729.c | 2 * Driver for the Cirrus PD6729 PCI-PCMCIA bridge. 16 #include <linux/interrupt.h> 29 MODULE_DESCRIPTION("Driver for the Cirrus PD6729 PCI-PCMCIA bridge"); 30 MODULE_AUTHOR("Jun Komuro <komurojun-mbn@nifty.com>"); 47 * Specifies the interrupt delivery mode. The default (1) is to use PCI 52 static int irq_mode = 1; /* 0 = ISA interrupt, 1 = PCI interrupt */ 56 "interrupt delivery mode. 0 = ISA, 1 = PCI. default is 1"); 70 reg += socket->number * 0x40; in indirect_read() 71 port = socket->io_base; in indirect_read() 87 reg = reg + socket->number * 0x40; in indirect_read16() [all …]
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/linux-3.3/drivers/gpio/ |
D | gpio-msm-v1.c | 3 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. 18 #include <linux/interrupt.h> 26 /* see 80-VA736-2 Rev C pp 695-751 32 ** Since the _BASE need to be page-aligned when we're mapping them 46 #define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ 47 #define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ 48 #define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ 49 #define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ 50 #define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */ 51 #define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */ [all …]
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/linux-3.3/arch/c6x/platforms/ |
D | megamod-pic.c | 2 * Support for C64x+ Megamodule Interrupt Controller 12 #include <linux/interrupt.h> 19 #include <asm/megamod-pic.h> 27 * Megamodule Interrupt Controller register layout 72 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in mask_megamod() 74 raw_spin_lock(&pic->lock); in mask_megamod() 76 raw_spin_unlock(&pic->lock); in mask_megamod() 83 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in unmask_megamod() 85 raw_spin_lock(&pic->lock); in unmask_megamod() 87 raw_spin_unlock(&pic->lock); in unmask_megamod() [all …]
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/linux-3.3/drivers/of/ |
D | irq.c | 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7 * Copyright (C) 1996-2001 Cort Dougan 17 * device tree to actual irq numbers on an interrupt controller 30 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space 31 * @device: Device node of the device whose interrupt is to be mapped 32 * @index: Index of the interrupt to map 50 * of_irq_find_parent - Given a device node, find its interrupt parent node 53 * Returns a pointer to the interrupt parent node, or NULL if the interrupt 65 parp = of_get_property(child, "interrupt-parent", NULL); in of_irq_find_parent() 76 } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL); in of_irq_find_parent() [all …]
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/linux-3.3/arch/blackfin/mach-bf561/include/mach/ |
D | defBF561.h | 2 * Copyright 2005-2010 Analog Devices Inc. 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 11 /* System MMR Register Map */ 14 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 16 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 17 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 18 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 19 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 20 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 29 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ [all …]
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/linux-3.3/arch/powerpc/boot/dts/fsl/ |
D | mpc8544si-post.dtsi | 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus"; 44 compatible = "fsl,mpc8540-pci"; 47 bus-range = <0 0xff>; 48 #interrupt-cells = <1>; 49 #size-cells = <2>; 50 #address-cells = <3>; 55 compatible = "fsl,mpc8548-pcie"; 57 #size-cells = <2>; [all …]
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D | p2020si-post.dtsi | 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; 44 compatible = "fsl,mpc8548-pcie"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0 255>; 49 clock-frequency = <33333333>; 54 #interrupt-cells = <1>; 55 #size-cells = <2>; [all …]
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D | mpc8572si-post.dtsi | 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 44 compatible = "fsl,mpc8548-pcie"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0 255>; 49 clock-frequency = <33333333>; 54 #interrupt-cells = <1>; 55 #size-cells = <2>; [all …]
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D | p3041si-post.dtsi | 36 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 44 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 clock-frequency = <33333333>; 53 #interrupt-cells = <1>; 54 #size-cells = <2>; [all …]
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D | p5020si-post.dtsi | 36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0x0 0xff>; 49 clock-frequency = <33333333>; 53 #interrupt-cells = <1>; 54 #size-cells = <2>; [all …]
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D | p1022si-post.dtsi | 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 44 compatible = "fsl,p1022-pcie"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0 255>; 49 clock-frequency = <33333333>; 54 #interrupt-cells = <1>; 55 #size-cells = <2>; [all …]
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/linux-3.3/arch/blackfin/mach-bf538/include/mach/ |
D | defBF538.h | 2 * Copyright 2008-2010 Analog Devices Inc. 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 10 /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ 11 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 12 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 13 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 14 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 15 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 23 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 24 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ [all …]
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/linux-3.3/arch/powerpc/boot/dts/ |
D | katmai.dts | 15 /dts-v1/; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 dcr-parent = <&{/cpus/cpu@0}>; 32 #address-cells = <1>; 33 #size-cells = <0>; 39 clock-frequency = <0>; /* Filled in by zImage */ 40 timebase-frequency = <0>; /* Filled in by zImage */ 41 i-cache-line-size = <32>; 42 d-cache-line-size = <32>; [all …]
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D | kilauea.dts | 4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 11 /dts-v1/; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */ 37 i-cache-line-size = <32>; [all …]
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D | p1023rds.dts | 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 6 * Author: Roy Zang <tie-fei.zang@freescale.com> 37 /include/ "fsl/p1023si-pre.dtsi" 42 #address-cells = <2>; 43 #size-cells = <2>; 44 interrupt-parent = <&mpic>; 62 #address-cells = <1>; 63 #size-cells = <1>; 66 spi-max-frequency = <40000000>; /* input clock */ 67 partition@u-boot { [all …]
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D | redwood.dts | 11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <1>; 18 dcr-parent = <&{/cpus/cpu@0}>; 26 #address-cells = <1>; 27 #size-cells = <0>; 33 clock-frequency = <0>; /* Filled in by U-Boot */ 34 timebase-frequency = <0>; /* Filled in by U-Boot */ 35 i-cache-line-size = <32>; 36 d-cache-line-size = <32>; [all …]
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D | mpc8544ds.dts | 12 /include/ "fsl/mpc8544si-pre.dtsi" 20 reg = <0 0 0 0>; // Filled by U-Boot 35 clock-frequency = <66666666>; 36 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 37 interrupt-map = < 101 * for interrupt-map & interrupt-map-mask 104 /include/ "fsl/mpc8544si-post.dtsi"
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D | mpc8377_wlan.dts | 4 * Copyright 2007-2009 Freescale Semiconductor Inc. 13 /dts-v1/; 17 #address-cells = <1>; 18 #size-cells = <1>; 31 #address-cells = <1>; 32 #size-cells = <0>; 37 d-cache-line-size = <32>; 38 i-cache-line-size = <32>; 39 d-cache-size = <32768>; 40 i-cache-size = <32768>; [all …]
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D | mpc8315erdb.dts | 12 /dts-v1/; 16 #address-cells = <1>; 17 #size-cells = <1>; 30 #address-cells = <1>; 31 #size-cells = <0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <16384>; 39 i-cache-size = <16384>; 40 timebase-frequency = <0>; // from bootloader [all …]
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D | currituck.dts | 11 /dts-v1/; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 dcr-parent = <&{/cpus/cpu@0}>; 27 #address-cells = <1>; 28 #size-cells = <0>; 34 clock-frequency = <1600000000>; // 1.6 GHz 35 timebase-frequency = <100000000>; // 100Mhz 36 i-cache-line-size = <32>; 37 d-cache-line-size = <32>; [all …]
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/linux-3.3/arch/mips/jazz/ |
D | irq.c | 7 * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle 12 #include <linux/interrupt.h> 29 unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START); in enable_r4030_irq() local 33 mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE); in enable_r4030_irq() 34 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask); in enable_r4030_irq() 40 unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START)); in disable_r4030_irq() local 44 mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE); in disable_r4030_irq() 45 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask); in disable_r4030_irq() 68 * On systems with i8259-style interrupt controllers we assume for 69 * driver compatibility reasons interrupts 0 - 15 to be the i8259 [all …]
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