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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
47 field bits<16> Inst;
61 bits<16> Inst;
63 let Inst{15-10} = 0x01;
64 let Inst{9-7} = rd;
65 let Inst{6-4} = rt;
66 let Inst{3-1} = rs;
67 let Inst{0} = funct;
75 bits<16> Inst;
77 let Inst{15-10} = funct;
[all …]
H A DMicroMips32r6InstrFormats.td40 bits<16> Inst;
42 let Inst{15-10} = 0x33;
43 let Inst{9-0} = offset;
50 bits<16> Inst;
52 let Inst{15-10} = op;
53 let Inst{9-7} = rs;
54 let Inst{6-0} = offset;
60 bits<16> Inst;
62 let Inst{15-10} = 0x11;
63 let Inst{9-5} = rs;
[all …]
H A DMipsMSAInstrFormats.td12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
48 let Inst{25-23} = major;
[all …]
H A DMipsInstrFormats.td74 field bits<32> Inst;
84 let Inst{31-26} = Opcode;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
179 bits<32> Inst;
181 let Inst{31-26} = op;
182 let Inst{25-0} = target;
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H A DMicroMipsDSPInstrFormats.td29 let Inst{31-26} = 0b000000;
30 let Inst{25-21} = rt;
31 let Inst{20-16} = rs;
32 let Inst{15-11} = rd;
33 let Inst{10-0} = op;
40 let Inst{31-26} = 0b000000;
41 let Inst{25-21} = rt;
42 let Inst{20-16} = rs;
43 let Inst{15-6} = op;
44 let Inst{5-0} = 0b111100;
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H A DMips32r6InstrFormats.td182 bits<32> Inst;
184 let Inst{31-26} = OPGROUP_AUI.Value;
185 let Inst{25-21} = rs;
186 let Inst{20-16} = rt;
187 let Inst{15-0} = imm;
191 let Inst{31-26} = OPGROUP_DAUI.Value;
197 bits<32> Inst;
199 let Inst{31-26} = OPGROUP_REGIMM.Value;
200 let Inst{25-21} = 0b00000;
201 let Inst{20-16} = OPCODE5_BGEZAL.Value;
[all …]
H A DMipsDSPInstrFormats.td72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
76 let Inst{5-0} = 0b010000;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
88 let Inst{10-6} = op;
89 let Inst{5-0} = 0b010000;
[all …]
/src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h30 constexpr RxC DecodeCR_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCR_RD() argument
31 constexpr RxC DecodeCI_RD(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCI_RD() argument
32 constexpr RxC DecodeCR_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCR_RS1() argument
33 constexpr RxC DecodeCI_RS1(uint32_t inst) { return RxC{DecodeRD(inst), false}; } in DecodeCI_RS1() argument
34 constexpr RxC DecodeCR_RS2(uint32_t inst) { in DecodeCR_RS2() argument
35 return RxC{(inst & 0x7C) >> 2, false}; in DecodeCR_RS2()
38 constexpr RxC DecodeCIW_RD(uint32_t inst) { return RxC{(inst & 0x1C) >> 2}; } in DecodeCIW_RD() argument
39 constexpr RxC DecodeCL_RD(uint32_t inst) { return RxC{DecodeCIW_RD(inst)}; } in DecodeCL_RD() argument
40 constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; } in DecodeCA_RD() argument
41 constexpr RxC DecodeCB_RD(uint32_t inst) { return RxC{DecodeCA_RD(inst)}; } in DecodeCB_RD() argument
[all …]
H A DEmulateInstructionRISCV.cpp70 constexpr uint32_t DecodeJImm(uint32_t inst) { in DecodeJImm() argument
71 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 11)) // imm[20] in DecodeJImm()
72 | (inst & 0xff000) // imm[19:12] in DecodeJImm()
73 | ((inst >> 9) & 0x800) // imm[11] in DecodeJImm()
74 | ((inst >> 20) & 0x7fe); // imm[10:1] in DecodeJImm()
77 constexpr uint32_t DecodeIImm(uint32_t inst) { in DecodeIImm() argument
78 return int64_t(int32_t(inst)) >> 20; // imm[11:0] in DecodeIImm()
81 constexpr uint32_t DecodeBImm(uint32_t inst) { in DecodeBImm() argument
82 return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 19)) // imm[12] in DecodeBImm()
83 | ((inst & 0x80) << 4) // imm[11] in DecodeBImm()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td13 let Inst{12-8} = Vu32{4-0};
15 let Inst{20-16} = Rt32{4-0};
17 let Inst{4-0} = Vdd32{4-0};
21 let Inst{11-5} = Ii{6-0};
23 let Inst{20-16} = Rs32{4-0};
25 let Inst{1-0} = Pd4{1-0};
29 let Inst{20-16} = Rss32{4-0};
31 let Inst{12-8} = Rt32{4-0};
33 let Inst{1-0} = Pd4{1-0};
37 let Inst{21-20} = Ii{10-9};
[all …]
/src/sys/crypto/openssl/aarch64/
H A Dchacha-armv8-sve.S40 .inst 0x04a0e3e5 //cntw x5, ALL, MUL #1
56 .inst 0x04aa4d3f //index z31.s,w9,w10
78 .inst 0x2599e3e0 //ptrues p0.s,ALL
98 .inst 0x05a03ae0 //dup z0.s,w23
99 .inst 0x05a03af9 //dup z25.s,w23
103 .inst 0x05a03904 //dup z4.s,w8
104 .inst 0x05a0391a //dup z26.s,w8
106 .inst 0x05a03b08 //dup z8.s,w24
107 .inst 0x05a03b1b //dup z27.s,w24
111 .inst 0x05a0394c //dup z12.s,w10
[all …]
H A Dsm4-armv8.S55 .inst 0xce70c800 //sm4ekey v0.4S,v0.4S,v16.4S
56 .inst 0xce71c801 //sm4ekey v1.4S,v0.4S,v17.4S
57 .inst 0xce72c822 //sm4ekey v2.4S,v1.4S,v18.4S
58 .inst 0xce73c843 //sm4ekey v3.4S,v2.4S,v19.4S
59 .inst 0xce74c864 //sm4ekey v4.4S,v3.4S,v20.4S
61 .inst 0xce75c885 //sm4ekey v5.4S,v4.4S,v21.4S
62 .inst 0xce76c8a6 //sm4ekey v6.4S,v5.4S,v22.4S
63 .inst 0xce77c8c7 //sm4ekey v7.4S,v6.4S,v23.4S
84 .inst 0xce70c8e7 //sm4ekey v7.4S,v7.4S,v16.4S
85 .inst 0xce71c8e6 //sm4ekey v6.4S,v7.4S,v17.4S
[all …]
H A Dsm3-armv8.S52 .inst 0xce63c004 //sm3partw1 v4.4s, v0.4s, v3.4s
53 .inst 0xce76c6e4 //sm3partw2 v4.4s, v23.4s, v22.4s
55 .inst 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
58 .inst 0xce5682e5 //sm3tt1a v5.4s, v23.4s, v22.4s[0]
59 .inst 0xce408ae6 //sm3tt2a v6.4s, v23.4s, v0.4s[0]
60 .inst 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
63 .inst 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
64 .inst 0xce409ae6 //sm3tt2a v6.4s, v23.4s, v0.4s[1]
65 .inst 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
68 .inst 0xce56a2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[2]
[all …]
/src/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp74 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
78 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
82 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
86 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
90 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
94 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
98 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
102 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
106 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
110 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
[all …]
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td15 field bits<32> Inst;
22 let Inst{0-5} = opcode;
92 field bits<64> Inst;
99 let Inst{0-5} = opcode1;
100 let Inst{32-37} = opcode2;
135 let Inst{6-29} = LI;
136 let Inst{30} = aa;
137 let Inst{31} = lk;
151 let Inst{6-10} = BIBO{4-0};
152 let Inst{11-15} = BI;
[all …]
/src/contrib/opencsd/decoder/source/i_dec/
H A Dtrc_idec_arminst.cpp45 int inst_ARM_is_direct_branch(uint32_t inst) in inst_ARM_is_direct_branch() argument
48 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_direct_branch()
50 if ((inst & 0xfe000000) == 0xfa000000){ in inst_ARM_is_direct_branch()
55 } else if ((inst & 0x0e000000) == 0x0a000000) { in inst_ARM_is_direct_branch()
63 int inst_ARM_wfiwfe(uint32_t inst) in inst_ARM_wfiwfe() argument
65 if ( ((inst & 0xf0000000) != 0xf0000000) && in inst_ARM_wfiwfe()
66 ((inst & 0x0ffffffe) == 0x0320f002) in inst_ARM_wfiwfe()
73 int inst_ARM_is_indirect_branch(uint32_t inst, struct decode_info *info) in inst_ARM_is_indirect_branch() argument
76 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_indirect_branch()
78 if ((inst & 0xfe500000) == 0xf8100000) { in inst_ARM_is_indirect_branch()
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/src/sys/crypto/openssl/arm/
H A Daesv8-armx.S10 # define INST(a,b,c,d) .byte c,d|0xc,a,b macro
13 # define INST(a,b,c,d) .byte a,b,c,d macro
58 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
77 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
92 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
124 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
160 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
176 INST(0x00,0x43,0xf0,0xf3) @ aese q10,q0
219 INST(0xc0,0x03,0xb0,0xf3) @ aesimc q0,q0
220 INST(0xc2,0x23,0xb0,0xf3) @ aesimc q1,q1
[all …]
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
31 let Inst{15-12} = funct4;
32 let Inst{11-7} = rs1;
33 let Inst{6-2} = rs2;
34 let Inst{1-0} = opcode;
38 // is responsible for setting the appropriate bits in the Inst field.
39 // The bits Inst{6-2} must be set for each instruction.
46 let Inst{15-13} = funct3;
47 let Inst{12} = imm{5};
48 let Inst{11-7} = rd;
[all …]
H A DRISCVInstrFormatsV.td63 let Inst{31} = 1;
64 let Inst{30} = 1;
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
80 let Inst{31} = 0;
81 let Inst{30-20} = vtypei;
82 let Inst{19-15} = rs1;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td13 let Inst{15} = 0;
14 let Inst{14 - 10} = sop;
15 let Inst{9 - 0} = offset;
22 let Inst{15} = 0;
23 let Inst{14 - 10} = sop;
24 let Inst{9 - 0} = offset;
33 let Inst{15 - 11} = 0b01011;
34 let Inst{10 - 8} = rx;
35 let Inst{7 - 5} = rz;
36 let Inst{4 - 2} = ry;
[all …]
H A DCSKYInstrFormats.td45 field bits<32> Inst;
46 let Inst{31 - 26} = opcode;
51 field bits<16> Inst;
61 let Inst{25 - 0} = offset;
72 let Inst{25 - 21} = rz;
73 let Inst{20 - 18} = sop;
74 let Inst{17 - 0} = offset;
86 let Inst{25 - 21} = rz;
87 let Inst{20 - 16} = rx;
88 let Inst{15 - 0} = imm16;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrFormats.td27 let Inst{31-0} = op;
28 let Inst{17-5} = imm13;
29 let Inst{4-0} = vd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = vj;
42 let Inst{4-0} = vd;
52 let Inst{31-0} = op;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = vd;
64 let Inst{31-0} = op;
[all …]
H A DLoongArchLASXInstrFormats.td27 let Inst{31-0} = op;
28 let Inst{17-5} = imm13;
29 let Inst{4-0} = xd;
40 let Inst{31-0} = op;
41 let Inst{9-5} = xj;
42 let Inst{4-0} = xd;
52 let Inst{31-0} = op;
53 let Inst{9-5} = rj;
54 let Inst{4-0} = xd;
64 let Inst{31-0} = op;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp42 static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
46 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
48 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
51 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
59 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
62 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
66 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
69 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
72 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
[all …]
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsLoongArch.td148 foreach inst = ["vadd_b", "vsub_b",
161 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty],
165 foreach inst = ["vadd_h", "vsub_h",
177 def int_loongarch_lsx_#inst : VecInt<[llvm_v8i16_ty],
181 foreach inst = ["vadd_w", "vsub_w",
193 def int_loongarch_lsx_#inst : VecInt<[llvm_v4i32_ty],
197 foreach inst = ["vadd_d", "vadd_q", "vsub_d", "vsub_q",
215 def int_loongarch_lsx_#inst : VecInt<[llvm_v2i64_ty],
219 foreach inst = ["vaddi_bu", "vsubi_bu",
228 def int_loongarch_lsx_#inst : VecInt<[llvm_v16i8_ty],
[all …]

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