Home
last modified time | relevance | path

Searched full:indexed (Results 1 – 25 of 58) sorted by relevance

123

/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc86 * Calculate and return the address for indexed mem operations:
342 * Load 64-bit float from indexed address.
362 * Store 64-bit float to indexed address.
555 * Load with memop from indexed address and add (imm5 << imm2) to rs1.
579 * Store with memop to indexed address and add (imm5 << imm2) to rs1.
736 * Load with memop from indexed address.
753 * Store with memop to indexed address.
/qemu/target/arm/tcg/
H A Dsve.decode558 # SVE broadcast indexed element
851 #### SVE Multiply - Indexed
853 # SVE integer dot product (indexed)
859 # SVE2 integer multiply-add (indexed)
867 # SVE2 saturating multiply-add high (indexed)
875 # SVE mixed sign dot product (indexed)
879 # SVE2 saturating multiply-add (indexed)
889 # SVE2 complex integer dot product (indexed)
895 # SVE2 complex integer multiply-add (indexed)
901 # SVE2 complex saturating integer multiply-add (indexed)
[all …]
H A Dtranslate-sme.c73 * For big-endian, adjust the indexed column byte offset within in get_tile_rowcol()
192 * Indexed by [esz][be][v][mte][st], which is (except for load/store) in trans_LDST1()
/qemu/include/hw/acpi/
H A Dacpi_dev_interface.h38 * for CPU indexed by @uid in @apic_ids array,
/qemu/include/hw/xen/interface/
H A Dphysdev.h35 * array indexed by Xen's PIRQ value.
42 * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
/qemu/docs/specs/
H A Dstandard-vga.rst80 port first), so indexed registers can be updated with a single
/qemu/docs/devel/
H A Dtcg.rst179 mappings change, all caches in QEMU are physically indexed. This
180 means that each basic block is indexed with its physical address.
/qemu/linux-user/include/host/loongarch64/
H A Dhost-signal.h64 case 0b001110: /* indexed, atomic, bounds-checking memory operations */ in host_signal_write()
/qemu/target/hexagon/
H A DREADME266 store_width width of stores (indexed by slot)
274 mem_log_stores record of the stores (indexed by slot)
/qemu/hw/nvram/
H A Dbcm2835_otp.c19 /* OTP rows are 1-indexed */
/qemu/tests/tcg/aarch64/system/
H A Dboot.S257 /* Stage 1 entry: indexed by IA[38:30] */
267 /* Stage 2 entries: indexed by IA[29:21] */
/qemu/hw/nvme/
H A Dnvme.h68 /* reclaim units indexed by reclaim group */
280 /* reclaim unit handle identifiers indexed by placement handle */
/qemu/include/qemu/
H A Dplugin.h125 /* A scoreboard is an array of values, indexed by vcpu_index */
/qemu/target/riscv/
H A Dpmu.c183 * started mode. Look at array being indexed with newprv.
186 * to inc. Look at arrays being indexed with env->priv.
/qemu/target/xtensa/
H A Dxtensa-isa-internal.h206 * we can get away with implementing lookups with tables indexed by
/qemu/tests/tcg/arm/system/
H A Dboot.S304 * 4096 entries, indexed by [31:20]
/qemu/ui/
H A Dvnc-enc-tight.h112 *-- The "palette" filter converts true-color pixel data to indexed colors
/qemu/target/s390x/
H A Dcpu_features.c240 /* indexed by feature group number for easy lookup */
/qemu/target/s390x/tcg/
H A Dvec_fpu_helper.c342 /* only the zero-indexed elements are compared */ in DEF_GVEC_VOP3()
362 /* only the zero-indexed elements are compared */ in wfc64()
382 /* only the zero-indexed elements are compared */ in wfc128()
/qemu/include/hw/intc/
H A Darm_gicv3_common.h93 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
/qemu/hw/display/
H A Dvga-pci.c101 * indexed registers with a single word write because the in pci_vga_ioport_write()
H A Dpl110.c116 /* Indexed by pl110_version */
H A Dati.c288 /* indexed access to regs or memory */ in ati_mm_read()
545 /* indexed access to regs or memory */ in ati_mm_write()
/qemu/scripts/
H A Dsimpletrace.py78 event_mapping (str -> Event): events dict, indexed by name
/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h152 * TLB way entries are virtually indexed.

123