xref: /linux/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml (revision 0cdee263bc5e7b20f657ea09f9272f50c568f35b) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: i.MX8QXP/QM JPEG decoder/encoder
8
9maintainers:
10  - Mirela Rabulea <mirela.rabulea@nxp.com>
11
12description: |-
13  The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
14  ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
15  and Extended Sequential DCT modes.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          enum:
22            - nxp,imx8qxp-jpgdec
23            - nxp,imx8qxp-jpgenc
24      - items:
25          - enum:
26              - nxp,imx8qm-jpgdec
27              - nxp,imx95-jpgdec
28          - const: nxp,imx8qxp-jpgdec
29      - items:
30          - enum:
31              - nxp,imx8qm-jpgenc
32              - nxp,imx95-jpgenc
33          - const: nxp,imx8qxp-jpgenc
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    items:
40      - description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
41      - description: IP bus clock for register access (ipg)
42
43  interrupts:
44    description: |
45      There are 4 slots available in the IP, which the driver may use
46      If a certain slot is used, it should have an associated interrupt
47      The interrupt with index i is assumed to be for slot i
48    minItems: 1               # At least one slot is needed by the driver
49    maxItems: 4               # The IP has 4 slots available for use
50
51  power-domains:
52    description:
53      List of phandle and PM domain specifier as documented in
54      Documentation/devicetree/bindings/power/power_domain.txt
55    minItems: 1               # Wrapper and all slots
56    maxItems: 5               # Wrapper and 4 slots
57
58required:
59  - compatible
60  - reg
61  - clocks
62  - interrupts
63  - power-domains
64
65allOf:
66  - if:
67      properties:
68        compatible:
69          contains:
70            enum:
71              - nxp,imx95-jpgenc
72              - nxp,imx95-jpgdec
73    then:
74      properties:
75        power-domains:
76          maxItems: 1
77    else:
78      properties:
79        power-domains:
80          minItems: 2        # Wrapper and 1 slot
81
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/imx8-lpcg.h>
88    #include <dt-bindings/interrupt-controller/arm-gic.h>
89    #include <dt-bindings/firmware/imx/rsrc.h>
90
91    jpegdec: jpegdec@58400000 {
92        compatible = "nxp,imx8qxp-jpgdec";
93        reg = <0x58400000 0x00050000 >;
94        clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
95                 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
96        interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
97                     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
98                     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
99                     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
100        power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
101                        <&pd IMX_SC_R_MJPEG_DEC_S0>,
102                        <&pd IMX_SC_R_MJPEG_DEC_S1>,
103                        <&pd IMX_SC_R_MJPEG_DEC_S2>,
104                        <&pd IMX_SC_R_MJPEG_DEC_S3>;
105    };
106
107    jpegenc: jpegenc@58450000 {
108        compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
109        reg = <0x58450000 0x00050000 >;
110        clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
111                 <&img_jpeg__lpcg IMX_LPCG_CLK_4>;
112        interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
116        power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
117                        <&pd IMX_SC_R_MJPEG_ENC_S0>,
118                        <&pd IMX_SC_R_MJPEG_ENC_S1>,
119                        <&pd IMX_SC_R_MJPEG_ENC_S2>,
120                        <&pd IMX_SC_R_MJPEG_ENC_S3>;
121    };
122...
123