/linux-5.10/arch/riscv/boot/dts/sifive/ |
D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; [all …]
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/linux-5.10/Documentation/devicetree/bindings/riscv/ |
D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V bindings for 'cpus' DT nodes 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 14 This document uses some terminology common to the RISC-V community 18 mandated by the RISC-V ISA: a PC and some registers. This 28 - items: 29 - enum: [all …]
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/linux-5.10/arch/arc/mm/ |
D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * TLB Management (flush/create/diagnostics) for ARC700 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue 11 * -No need to flush_cache_page( ) for each call to update_mmu_cache() 13 * = page-fault thrice as fast (75 usec to 28 usec) 18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 22 * -MMU v2/v3 BCRs decoded differently 23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512 24 * -tlb_entry_erase( ) can be void [all …]
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/linux-5.10/arch/powerpc/include/asm/nohash/32/ |
D | pte-44x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 9 * Because of the 3 word TLB entries to support 36-bit addressing, 11 * are easily loaded during exception processing. I decided to 16 * ERPN fields in the TLB. -Matt 19 * easier to move into the TLB from the PTE. -BenH. 25 * PPC 440 core has following TLB attribute fields; 29 * RPN................................. - - - - - - ERPN....... 33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR 43 * into TLB entry. 45 * - PRESENT *must* be in the bottom three bits because swap cache [all …]
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D | pte-fsl-booke.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based 14 - PRESENT *must* be in the bottom three bits because swap cache 19 /* Definitions for FSL Book-E Cores */ 30 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ 52 * We define 2 sets of base prot bits, one for basic pages (ie,
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/linux-5.10/arch/openrisc/mm/ |
D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * OpenRISC tlb.c 11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se> 12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 29 #define NO_CONTEXT -1 35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1)) 36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1)) 38 * Invalidate all TLB entries. 48 int i; in local_flush_tlb_all() local 51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all() [all …]
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/linux-5.10/arch/powerpc/kernel/ |
D | setup_64.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 61 #include <asm/code-patching.h> 66 #include <asm/feature-fixups.h> 99 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data() 101 * set up this TLB. in setup_tlb_core_data() 106 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data() 110 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data() 126 /* Look for ibm,smt-enabled OF option */ 153 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled() 168 /* Look for smt-enabled= cmdline option */ [all …]
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/linux-5.10/arch/parisc/include/asm/ |
D | ropes.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 5 #include <asm/parisc-device.h> 8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */ 30 void __iomem *ioc_hpa; /* I/O MMU base address */ 33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */ 34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */ 38 unsigned long *res_hint; /* next avail IOVP - circular search */ 85 unsigned int num_ioc; /* number of on-board IOC's */ 96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO() 100 return d->id.hversion == IKE_MERCED_PORT; in IS_IKE() [all …]
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/linux-5.10/arch/mips/kvm/ |
D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that 7 * TLB handlers run from KSEG0 26 #include <asm/tlb.h> 46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid() 57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid() 65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid() 71 /* Structure defining an tlb entry data set. */ 90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs() 91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local 92 int i; in kvm_mips_dump_guest_tlbs() local [all …]
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/linux-5.10/arch/powerpc/mm/ |
D | init_32.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com) 38 #include <asm/tlb.h> 47 /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */ 48 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - PAGE_OFFSET)) 75 * (i.e. page tables) instead of the bats. 76 * -- Cort 85 * Check for command-line options that affect what MMU_init will do. 108 * MMU_init sets up the basic memory mappings for the kernel, [all …]
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/linux-5.10/arch/powerpc/mm/book3s64/ |
D | radix_tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * TLB flush routines for radix kernels. 5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. 14 #include <asm/ppc-opcode.h> 15 #include <asm/tlb.h> 27 * i.e., r=1 and is=01 or is=10 or is=11 40 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300() 51 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300() 52 * and partition table entries. Then flush the remaining sets of the in tlbiel_all_isa300() 53 * TLB. in tlbiel_all_isa300() [all …]
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D | hash_native.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 23 #include <asm/tlb.h> 27 #include <asm/ppc-opcode.h> 28 #include <asm/feature-fixups.h> 30 #include <misc/cxl-base.h> 57 * i.e., r=1 and is=01 or is=10 or is=11 71 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r) in tlbiel_hash_set_isa300() 107 * * PRS=1, R=0, and RIC!=2 (The only process-scoped in tlbiel_all_isa300() 113 * Then flush the sets of the TLB proper. Hash mode uses in tlbiel_all_isa300() 114 * partition scoped TLB translations, which may be flushed in tlbiel_all_isa300() [all …]
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/linux-5.10/arch/arm/mm/ |
D | proc-arm720.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720 8 * hacked for non-paged-MM by Hyok S. Choi, 2004. 10 * These are the low level assembler for performing cache and TLB 15 * 05-09-2000 SJH Created by moving 720 specific functions 16 * out of 'proc-arm6,7.S' per RMK discussion 17 * 07-25-2000 SJH Added idle function. 18 * 08-25-2000 DBS Updated for integration of ARM Ltd version. 19 * 04-20-2004 HSC modified for non-paged memory management mode. 25 #include <asm/asm-offsets.h> [all …]
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/linux-5.10/include/asm-generic/ |
D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* include/asm-generic/tlb.h 4 * Generic TLB shootdown code 32 * Generic MMU-gather implementation. 35 * correct and efficient ordering of freeing pages and TLB invalidations. 40 * 2) TLB invalidate page 49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather 51 * Finish in particular will issue a (final) TLB invalidate and free 54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA 59 * - tlb_remove_table() [all …]
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/linux-5.10/arch/powerpc/kvm/ |
D | e500_mmu_host.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All rights reserved. 30 #include <asm/pte-walk.h> 38 #define to_htlb1_esel(esel) (host_tlb_params[1].entries - (esel) - 1) 45 return host_tlb_params[1].entries - tlbcam_index - 1; in tlb1_max_shadow_size() 67 * writing shadow tlb entry to host TLB 77 mtspr(SPRN_MAS1, stlbe->mas1); in __write_host_tlbe() 78 mtspr(SPRN_MAS2, (unsigned long)stlbe->mas2); in __write_host_tlbe() 79 mtspr(SPRN_MAS3, (u32)stlbe->mas7_3); in __write_host_tlbe() 80 mtspr(SPRN_MAS7, (u32)(stlbe->mas7_3 >> 32)); in __write_host_tlbe() [all …]
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/linux-5.10/arch/x86/mm/ |
D | pgtable.c | 1 // SPDX-License-Identifier: GPL-2.0 6 #include <asm/tlb.h> 11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1; 23 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument 25 tlb_remove_page(tlb, table); in paravirt_tlb_remove_table() 39 return -EINVAL; in setup_userpte() 48 return -EINVAL; in setup_userpte() 53 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument 57 paravirt_tlb_remove_table(tlb, pte); in ___pte_free_tlb() 61 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument [all …]
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/linux-5.10/Documentation/x86/ |
D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0 19 application page-faults. For more information please refer to the PCIe 25 mmu_notifier() support to keep the device TLB cache and the CPU cache in 34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits 40 ID (PASID), which is a 20-bit number defined by the PCIe SIG. 43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe 55 ENQCMD works with non-posted semantics and carries a status back if the 62 to perform I/O operations via use of PASID. 67 A new thread-scoped MSR (IA32_PASID) provides the connection between 69 accesses an SVA-capable device, this MSR is initialized with a newly [all …]
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/linux-5.10/arch/nds32/kernel/ |
D | setup.c | 1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2005-2017 Andes Technology Corporation 10 #include <linux/dma-mapping.h> 15 #include <asm/proc-fns.h> 92 int i, p = 0; in dump_cpu_info() local 95 for (i = 0; hwcap_str[i]; i++) { in dump_cpu_info() 96 if (elf_hwcap & (1 << i)) { in dump_cpu_info() 97 sprintf(str + p, "%s ", hwcap_str[i]); in dump_cpu_info() 98 p += strlen(hwcap_str[i]) + 1; in dump_cpu_info() 106 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); in dump_cpu_info() [all …]
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/linux-5.10/drivers/parisc/ |
D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 ** ccio-dma.c: 4 ** DMA management routines for first generation cache-coherent machines. 5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 9 ** (c) Copyright 2000 Hewlett-Packard Company 15 ** the I/O MMU - basically what x86 does. 17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. [all …]
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/linux-5.10/arch/powerpc/include/asm/ |
D | mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 8 #include <asm/asm-const.h> 63 /* Enable >32-bit physical addresses on 32-bit processor, only used 68 /* Enable use of broadcast TLB invalidations. We don't always set it 90 /* Enable use of TLB reservation. Processor should support tlbsrx. 128 /* MMU feature bit sets for various CPUs */ 206 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); in early_mmu_has_feature() 220 int i; in mmu_has_feature() local 237 i = __builtin_ctzl(feature); in mmu_has_feature() 238 return static_branch_likely(&mmu_feature_keys[i]); in mmu_has_feature() [all …]
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/linux-5.10/arch/parisc/mm/ |
D | fault.c | 37 * parisc_acctyp(unsigned int inst) -- 38 * Given a PA-RISC memory access instruction, determine if the 43 * instruction (i.e. you should really only call it if you know that 79 * older PA-RISC platforms. The case where a block in parisc_acctyp() 87 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp() 88 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp() 89 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp() 104 * Data TLB miss fault/data page fault in parisc_acctyp() 125 * not, but I want it committed to CVS so I don't lose it :-) 128 if (tree->vm_start > addr) { [all …]
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/linux-5.10/arch/parisc/include/uapi/asm/ |
D | pdc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/ 15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */ 16 #define PDC_ERROR -3 /* Call could not complete without an error */ 17 #define PDC_NE_MOD -5 /* Module not found */ 18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */ 19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */ 20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */ 21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */ 22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */ [all …]
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/linux-5.10/arch/powerpc/include/asm/book3s/64/ |
D | mmu-hash.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 13 #include <asm/asm-const.h> 46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ 128 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ 129 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ 130 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */ 131 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */ 192 return -1; in shift_to_mmu_psize() 211 return -1; in ap_to_shift() 249 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) argument [all …]
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/linux-5.10/arch/mips/mm/ |
D | c-octeon.c | 6 * Copyright (C) 2005-2007 Cavium Networks 20 #include <asm/cpu-features.h> 21 #include <asm/cpu-type.h> 34 * Octeon automatically flushes the dcache on tlb changes, so 50 * Flush local I-cache for the specified range. 83 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores() 139 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range() 154 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_page() 179 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon() 180 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon() [all …]
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/linux-5.10/arch/microblaze/include/asm/ |
D | pgtable.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2008-2009 PetaLogix 51 * Sort of meaningless for non-VM targets. 58 #include <asm-generic/pgtable-nopmd.h> 103 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 107 * We use the hash table as an extended TLB, i.e. a cache of currently 108 * active mappings. We maintain a two-level page table tree, much 110 * management code. Low-level assembler code in hashtable.S 117 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The [all …]
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